..
AsmParser
InstPrinter
[cleanup] Re-sort all the #include lines in LLVM using
2015-01-14 11:23:27 +00:00
MCTargetDesc
Add r224985 back with fixes.
2015-01-19 21:11:14 +00:00
TargetInfo
AMDGPU.h
R600/SI: Use external symbols for scratch buffer
2015-01-20 17:49:47 +00:00
AMDGPU.td
R600/SI: Add subtarget feature for if f32 fma is fast
2015-01-29 19:34:25 +00:00
AMDGPUAlwaysInlinePass.cpp
AMDGPUAsmPrinter.cpp
Compute the ELF SectionKind from the flags.
2015-01-29 17:33:21 +00:00
AMDGPUAsmPrinter.h
std::unique_ptrify the MCStreamer argument to createAsmPrinter
2015-01-18 20:29:04 +00:00
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp
R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
2015-01-15 18:42:51 +00:00
AMDGPUInstrInfo.h
R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
2015-01-15 18:42:51 +00:00
AMDGPUInstrInfo.td
AMDGPUInstructions.td
R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
2015-01-15 23:58:35 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp
R600/SI: Move i64 -> v2i32 load promotion into AMDGPUDAGToDAGISel::Select()
2015-01-23 22:05:45 +00:00
AMDGPUISelLowering.cpp
Move DataLayout back to the TargetMachine from TargetSubtargetInfo
2015-01-26 19:03:15 +00:00
AMDGPUISelLowering.h
R600: Try to use lower types for 64bit division if possible
2015-01-22 23:42:43 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp
R600/SI: Use external symbols for scratch buffer
2015-01-20 17:49:47 +00:00
AMDGPUMCInstLower.h
R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
2015-01-15 18:42:51 +00:00
AMDGPUPromoteAlloca.cpp
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp
R600/SI: Add subtarget feature for if f32 fma is fast
2015-01-29 19:34:25 +00:00
AMDGPUSubtarget.h
R600/SI: Add subtarget feature for if f32 fma is fast
2015-01-29 19:34:25 +00:00
AMDGPUTargetMachine.cpp
R600: Move DataLayout to AMDGPUTargetMachine
2015-01-28 16:04:26 +00:00
AMDGPUTargetMachine.h
R600: Move DataLayout to AMDGPUTargetMachine
2015-01-28 16:04:26 +00:00
AMDGPUTargetTransformInfo.cpp
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h
CaymanInstructions.td
CIInstructions.td
CMakeLists.txt
R600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 15:42:31 +00:00
EvergreenInstructions.td
R600/SI: Custom lower fround
2015-01-21 18:18:25 +00:00
LLVMBuild.txt
Makefile
Processors.td
R600/SI: Add subtarget feature for if f32 fma is fast
2015-01-29 19:34:25 +00:00
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td
R600/SI: Custom lower fround
2015-01-21 18:18:25 +00:00
R600Intrinsics.td
R600ISelLowering.cpp
[SelectionDAG] Allow targets to specify legality of extloads' result
2015-01-08 00:51:32 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp
SIDefines.h
R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
2015-01-20 19:33:04 +00:00
SIFixSGPRCopies.cpp
R600/SI: Remove VReg_32 register class
2015-01-07 20:59:25 +00:00
SIFixSGPRLiveRanges.cpp
SIFoldOperands.cpp
R600/SI: Add pattern for bitcasting fp immediates to integers
2015-01-13 22:59:41 +00:00
SIInsertWaits.cpp
SIInstrFormats.td
R600/SI: Add VI versions of LDS atomics
2015-01-27 17:25:07 +00:00
SIInstrInfo.cpp
R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
2015-01-20 19:33:04 +00:00
SIInstrInfo.h
R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
2015-01-15 18:42:51 +00:00
SIInstrInfo.td
R600/SI: Don't set patterns for chip-specific instructions while having pseudos
2015-01-27 17:25:11 +00:00
SIInstructions.td
R600/SI: Fix MIN3/MAX3 on VI, define MED3
2015-01-27 17:25:15 +00:00
SIIntrinsics.td
SIISelLowering.cpp
R600/SI: Implement enableAggressiveFMAFusion
2015-01-29 19:34:32 +00:00
SIISelLowering.h
R600/SI: Implement enableAggressiveFMAFusion
2015-01-29 19:34:32 +00:00
SILoadStoreOptimizer.cpp
SILowerControlFlow.cpp
R600/SI: Add pattern for bitcasting fp immediates to integers
2015-01-13 22:59:41 +00:00
SILowerI1Copies.cpp
R600/SI: Remove VReg_32 register class
2015-01-07 20:59:25 +00:00
SIMachineFunctionInfo.cpp
R600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 15:42:31 +00:00
SIMachineFunctionInfo.h
R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
2015-01-20 19:33:04 +00:00
SIPrepareScratchRegs.cpp
R600/SI: Fix simple-loop.ll test
2015-01-20 19:33:02 +00:00
SIRegisterInfo.cpp
R600/SI: Remove stray debug statements
2015-01-29 16:55:28 +00:00
SIRegisterInfo.h
R600/SI: Define a schedule model and enable the generic machine scheduler
2015-01-29 16:55:25 +00:00
SIRegisterInfo.td
R600/SI: Use RegisterOperands to specify which operands can accept immediates
2015-01-12 19:33:18 +00:00
SISchedule.td
R600/SI: Define a schedule model
2015-01-14 01:13:19 +00:00
SIShrinkInstructions.cpp
R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
2015-01-15 18:42:51 +00:00
SITypeRewriter.cpp
VIInstrFormats.td
VIInstructions.td
R600/SI: Add VI versions of MUBUF loads and stores
2015-01-27 17:24:58 +00:00
