mirror of
https://github.com/c64scene-ar/llvm-6502.git
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e3d3572e28
make the addend fixup code a bit more generic Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145998 91177308-0d34-0410-b5e6-96231b3b80d8
300 lines
10 KiB
C++
300 lines
10 KiB
C++
//===-- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower Mips MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsAsmPrinter.h"
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#include "MipsInstrInfo.h"
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#include "MipsMCInstLower.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Target/Mangler.h"
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using namespace llvm;
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MipsMCInstLower::MipsMCInstLower(Mangler *mang, const MachineFunction &mf,
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MipsAsmPrinter &asmprinter)
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: Ctx(mf.getContext()), Mang(mang), AsmPrinter(asmprinter) {}
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MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
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MachineOperandType MOTy,
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unsigned Offset) const {
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MCSymbolRefExpr::VariantKind Kind;
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const MCSymbol *Symbol;
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switch(MO.getTargetFlags()) {
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default: assert(0 && "Invalid target flag!");
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case MipsII::MO_NO_FLAG: Kind = MCSymbolRefExpr::VK_None; break;
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case MipsII::MO_GPREL: Kind = MCSymbolRefExpr::VK_Mips_GPREL; break;
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case MipsII::MO_GOT_CALL: Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break;
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case MipsII::MO_GOT16: Kind = MCSymbolRefExpr::VK_Mips_GOT16; break;
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case MipsII::MO_GOT: Kind = MCSymbolRefExpr::VK_Mips_GOT; break;
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case MipsII::MO_ABS_HI: Kind = MCSymbolRefExpr::VK_Mips_ABS_HI; break;
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case MipsII::MO_ABS_LO: Kind = MCSymbolRefExpr::VK_Mips_ABS_LO; break;
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case MipsII::MO_TLSGD: Kind = MCSymbolRefExpr::VK_Mips_TLSGD; break;
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case MipsII::MO_GOTTPREL: Kind = MCSymbolRefExpr::VK_Mips_GOTTPREL; break;
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case MipsII::MO_TPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_TPREL_HI; break;
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case MipsII::MO_TPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_TPREL_LO; break;
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case MipsII::MO_GPOFF_HI: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_HI; break;
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case MipsII::MO_GPOFF_LO: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_LO; break;
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case MipsII::MO_GOT_DISP: Kind = MCSymbolRefExpr::VK_Mips_GOT_DISP; break;
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case MipsII::MO_GOT_PAGE: Kind = MCSymbolRefExpr::VK_Mips_GOT_PAGE; break;
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case MipsII::MO_GOT_OFST: Kind = MCSymbolRefExpr::VK_Mips_GOT_OFST; break;
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}
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switch (MOTy) {
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case MachineOperand::MO_MachineBasicBlock:
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Symbol = MO.getMBB()->getSymbol();
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break;
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case MachineOperand::MO_GlobalAddress:
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Symbol = Mang->getSymbol(MO.getGlobal());
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break;
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case MachineOperand::MO_BlockAddress:
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Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress());
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break;
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case MachineOperand::MO_ExternalSymbol:
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Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName());
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break;
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case MachineOperand::MO_JumpTableIndex:
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Symbol = AsmPrinter.GetJTISymbol(MO.getIndex());
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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Symbol = AsmPrinter.GetCPISymbol(MO.getIndex());
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if (MO.getOffset())
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Offset += MO.getOffset();
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break;
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default:
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llvm_unreachable("<unknown operand type>");
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}
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const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, Ctx);
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if (!Offset)
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return MCOperand::CreateExpr(MCSym);
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// Assume offset is never negative.
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assert(Offset > 0);
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const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx);
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const MCBinaryExpr *AddExpr = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, Ctx);
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return MCOperand::CreateExpr(AddExpr);
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}
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// Lower ".cpload $reg" to
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// "lui $gp, %hi(_gp_disp)"
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// "addiu $gp, $gp, %lo(_gp_disp)"
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// "addu $gp. $gp, $reg"
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void MipsMCInstLower::LowerCPLOAD(const MachineInstr *MI,
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SmallVector<MCInst, 4>& MCInsts) {
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MCInst Lui, Addiu, Addu;
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StringRef SymName("_gp_disp");
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const MCSymbol *Symbol = Ctx.GetOrCreateSymbol(SymName);
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const MCSymbolRefExpr *MCSym;
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// lui $gp, %hi(_gp_disp)
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Lui.setOpcode(Mips::LUi);
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Lui.addOperand(MCOperand::CreateReg(Mips::GP));
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MCSym = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_Mips_ABS_HI, Ctx);
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Lui.addOperand(MCOperand::CreateExpr(MCSym));
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MCInsts.push_back(Lui);
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// addiu $gp, $gp, %lo(_gp_disp)
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Addiu.setOpcode(Mips::ADDiu);
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Addiu.addOperand(MCOperand::CreateReg(Mips::GP));
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Addiu.addOperand(MCOperand::CreateReg(Mips::GP));
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MCSym = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_Mips_ABS_LO, Ctx);
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Addiu.addOperand(MCOperand::CreateExpr(MCSym));
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MCInsts.push_back(Addiu);
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// addu $gp. $gp, $reg
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Addu.setOpcode(Mips::ADDu);
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Addu.addOperand(MCOperand::CreateReg(Mips::GP));
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Addu.addOperand(MCOperand::CreateReg(Mips::GP));
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const MachineOperand &MO = MI->getOperand(0);
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assert(MO.isReg() && "CPLOAD's operand must be a register.");
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Addu.addOperand(MCOperand::CreateReg(MO.getReg()));
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MCInsts.push_back(Addu);
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}
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// Lower ".cprestore offset" to "sw $gp, offset($sp)".
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void MipsMCInstLower::LowerCPRESTORE(const MachineInstr *MI, MCInst &OutMI) {
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OutMI.clear();
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OutMI.setOpcode(Mips::SW);
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OutMI.addOperand(MCOperand::CreateReg(Mips::GP));
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OutMI.addOperand(MCOperand::CreateReg(Mips::SP));
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const MachineOperand &MO = MI->getOperand(0);
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assert(MO.isImm() && "CPRESTORE's operand must be an immediate.");
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OutMI.addOperand(MCOperand::CreateImm(MO.getImm()));
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}
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MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO,
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unsigned offset) const {
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MachineOperandType MOTy = MO.getType();
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switch (MOTy) {
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default:
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assert(0 && "unknown operand type");
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break;
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit()) break;
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return MCOperand::CreateReg(MO.getReg());
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case MachineOperand::MO_Immediate:
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return MCOperand::CreateImm(MO.getImm() + offset);
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case MachineOperand::MO_MachineBasicBlock:
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case MachineOperand::MO_GlobalAddress:
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case MachineOperand::MO_ExternalSymbol:
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case MachineOperand::MO_JumpTableIndex:
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case MachineOperand::MO_ConstantPoolIndex:
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case MachineOperand::MO_BlockAddress:
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return LowerSymbolOperand(MO, MOTy, offset);
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}
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return MCOperand();
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}
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void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCOp = LowerOperand(MO);
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if (MCOp.isValid())
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OutMI.addOperand(MCOp);
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}
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}
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void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
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SmallVector<MCInst,
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4>& MCInsts) {
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unsigned Opc = MI->getOpcode();
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MCInst instr1, instr2, instr3, move;
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bool two_instructions = false;
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assert(MI->getNumOperands() == 3);
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assert(MI->getOperand(0).isReg());
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assert(MI->getOperand(1).isReg());
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MCOperand target = LowerOperand(MI->getOperand(0));
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MCOperand base = LowerOperand(MI->getOperand(1));
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MCOperand atReg = MCOperand::CreateReg(Mips::AT);
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MCOperand zeroReg = MCOperand::CreateReg(Mips::ZERO);
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MachineOperand unloweredName = MI->getOperand(2);
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MCOperand name = LowerOperand(unloweredName);
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move.setOpcode(Mips::ADDu);
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move.addOperand(target);
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move.addOperand(atReg);
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move.addOperand(zeroReg);
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switch (Opc) {
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case Mips::ULW: {
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// FIXME: only works for little endian right now
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MCOperand adj_name = LowerOperand(unloweredName, 3);
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if (base.getReg() == (target.getReg())) {
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instr1.setOpcode(Mips::LWL);
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instr1.addOperand(atReg);
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instr1.addOperand(base);
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instr1.addOperand(adj_name);
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instr2.setOpcode(Mips::LWR);
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instr2.addOperand(atReg);
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instr2.addOperand(base);
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instr2.addOperand(name);
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instr3 = move;
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} else {
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two_instructions = true;
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instr1.setOpcode(Mips::LWL);
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instr1.addOperand(target);
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instr1.addOperand(base);
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instr1.addOperand(adj_name);
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instr2.setOpcode(Mips::LWR);
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instr2.addOperand(target);
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instr2.addOperand(base);
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instr2.addOperand(name);
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}
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break;
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}
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case Mips::ULHu: {
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// FIXME: only works for little endian right now
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MCOperand adj_name = LowerOperand(unloweredName, 1);
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instr1.setOpcode(Mips::LBu);
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instr1.addOperand(atReg);
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instr1.addOperand(base);
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instr1.addOperand(adj_name);
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instr2.setOpcode(Mips::LBu);
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instr2.addOperand(target);
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instr2.addOperand(base);
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instr2.addOperand(name);
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instr3.setOpcode(Mips::INS);
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instr3.addOperand(target);
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instr3.addOperand(atReg);
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instr3.addOperand(MCOperand::CreateImm(0x8));
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instr3.addOperand(MCOperand::CreateImm(0x18));
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break;
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}
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case Mips::USW: {
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// FIXME: only works for little endian right now
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assert (base.getReg() != target.getReg());
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two_instructions = true;
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MCOperand adj_name = LowerOperand(unloweredName, 3);
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instr1.setOpcode(Mips::SWL);
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instr1.addOperand(target);
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instr1.addOperand(base);
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instr1.addOperand(adj_name);
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instr2.setOpcode(Mips::SWR);
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instr2.addOperand(target);
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instr2.addOperand(base);
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instr2.addOperand(name);
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break;
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}
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case Mips::USH: {
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MCOperand adj_name = LowerOperand(unloweredName, 1);
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instr1.setOpcode(Mips::SB);
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instr1.addOperand(target);
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instr1.addOperand(base);
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instr1.addOperand(name);
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instr2.setOpcode(Mips::SRL);
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instr2.addOperand(atReg);
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instr2.addOperand(target);
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instr2.addOperand(MCOperand::CreateImm(8));
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instr3.setOpcode(Mips::SB);
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instr3.addOperand(atReg);
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instr3.addOperand(base);
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instr3.addOperand(adj_name);
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break;
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}
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default:
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// FIXME: need to add others
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assert(0 && "unaligned instruction not processed");
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}
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MCInsts.push_back(instr1);
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MCInsts.push_back(instr2);
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if (!two_instructions) MCInsts.push_back(instr3);
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}
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