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https://github.com/c64scene-ar/llvm-6502.git
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532dc2e1f2
register ordering, for both physical and virtual registers. Update the PPC target lowering for calls to expect registers for the call result to already be in target order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38471 91177308-0d34-0410-b5e6-96231b3b80d8
14 lines
314 B
LLVM
14 lines
314 B
LLVM
; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
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; RUN: grep {addic 4, 4, 1}
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; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
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; RUN: grep {addze 3, 3}
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declare i64 @foo();
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define i64 @bar()
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{
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%t = call i64 @foo()
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%s = add i64 %t, 1
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ret i64 %s
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}
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