Tim Northover ca396e391e IR: add a second ordering operand to cmpxhg for failure ... The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203559 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-11 10:48:52 +00:00
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AArch64	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
ARM	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
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Mips	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
MSP430
NVPTX	Followup to r203483 - add test.	2014-03-10 20:36:04 +00:00
PowerPC	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
R600	R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCC	2014-03-07 20:12:39 +00:00
SPARC	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
SystemZ	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
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X86	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
XCore	[XCore] Add support for the "m" inline asm constraint.	2014-03-06 16:37:48 +00:00