llvm-6502/test/CodeGen/ARM/ldrd.ll
Jakob Stoklund Olesen ca6fd009ad Fix ARM tests to be register allocator independent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 22:14:03 +00:00

25 lines
630 B
LLVM

; RUN: llc < %s -mtriple=armv6-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V6
; RUN: llc < %s -mtriple=armv5-apple-darwin | FileCheck %s -check-prefix=V5
; RUN: llc < %s -mtriple=armv6-eabi | FileCheck %s -check-prefix=EABI
; rdar://r6949835
; Magic ARM pair hints works best with linearscan.
@b = external global i64*
define i64 @t(i64 %a) nounwind readonly {
entry:
;V6: ldrd r2, [r2]
;V5: ldr r{{[0-9]+}}, [r2]
;V5: ldr r{{[0-9]+}}, [r2, #4]
;EABI: ldr r{{[0-9]+}}, [r2]
;EABI: ldr r{{[0-9]+}}, [r2, #4]
%0 = load i64** @b, align 4
%1 = load i64* %0, align 4
%2 = mul i64 %1, %a
ret i64 %2
}