Colin LeMahieu ca96263b05 [Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225201 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-05 20:56:41 +00:00
..
Analysis	[PM] Don't run the machinery of invalidating all the analysis passes	2015-01-05 12:32:11 +00:00
AsmParser
Bitcode	[PM] Switch the new pass manager to use a reference-based API for IR	2015-01-05 02:47:05 +00:00
CodeGen	Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert.	2015-01-05 10:15:49 +00:00
DebugInfo
ExecutionEngine
IR	IR: Prune arguments to ValueAsMetadata::ValueAsMetadata()	2015-01-05 20:41:25 +00:00
IRReader
LineEditor
Linker
LTO
MC
Object
Option
ProfileData
Support	[APFloat][ADT] Fix sign handling logic for FMA results that truncate to zero.	2015-01-04 01:20:55 +00:00
TableGen
Target	[Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts.	2015-01-05 20:56:41 +00:00
Transforms	SymbolRewriter: use iplist::splice	2015-01-05 17:56:32 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile