llvm-6502/lib/Target/MSP430/MSP430RegisterInfo.td
Jakob Stoklund Olesen ca561ffcf3 Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:27:12 +00:00

120 lines
4.0 KiB
TableGen

//===- MSP430RegisterInfo.td - MSP430 Register defs ----------*- tblgen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Declarations that describe the MSP430 register file
//===----------------------------------------------------------------------===//
class MSP430Reg<bits<4> num, string n> : Register<n> {
field bits<4> Num = num;
let Namespace = "MSP430";
}
class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs>
: RegisterWithSubRegs<n, subregs> {
field bits<4> Num = num;
let Namespace = "MSP430";
}
//===----------------------------------------------------------------------===//
// Registers
//===----------------------------------------------------------------------===//
def PCB : MSP430Reg<0, "r0">;
def SPB : MSP430Reg<1, "r1">;
def SRB : MSP430Reg<2, "r2">;
def CGB : MSP430Reg<3, "r3">;
def FPB : MSP430Reg<4, "r4">;
def R5B : MSP430Reg<5, "r5">;
def R6B : MSP430Reg<6, "r6">;
def R7B : MSP430Reg<7, "r7">;
def R8B : MSP430Reg<8, "r8">;
def R9B : MSP430Reg<9, "r9">;
def R10B : MSP430Reg<10, "r10">;
def R11B : MSP430Reg<11, "r11">;
def R12B : MSP430Reg<12, "r12">;
def R13B : MSP430Reg<13, "r13">;
def R14B : MSP430Reg<14, "r14">;
def R15B : MSP430Reg<15, "r15">;
def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; }
let SubRegIndices = [subreg_8bit] in {
def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>;
def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>;
def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>;
def CGW : MSP430RegWithSubregs<3, "r3", [CGB]>;
def FPW : MSP430RegWithSubregs<4, "r4", [FPB]>;
def R5W : MSP430RegWithSubregs<5, "r5", [R5B]>;
def R6W : MSP430RegWithSubregs<6, "r6", [R6B]>;
def R7W : MSP430RegWithSubregs<7, "r7", [R7B]>;
def R8W : MSP430RegWithSubregs<8, "r8", [R8B]>;
def R9W : MSP430RegWithSubregs<9, "r9", [R9B]>;
def R10W : MSP430RegWithSubregs<10, "r10", [R10B]>;
def R11W : MSP430RegWithSubregs<11, "r11", [R11B]>;
def R12W : MSP430RegWithSubregs<12, "r12", [R12B]>;
def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>;
def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>;
def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>;
}
def GR8 : RegisterClass<"MSP430", [i8], 8,
// Volatile registers
[R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,
// Frame pointer, sometimes allocable
FPB,
// Volatile, but not allocable
PCB, SPB, SRB, CGB]>
{
let MethodProtos = [{
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
GR8Class::iterator
GR8Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetRegisterInfo *RI = TM.getRegisterInfo();
// Depending on whether the function uses frame pointer or not, last 5 or 4
// registers on the list above are reserved
if (RI->hasFP(MF))
return end()-5;
else
return end()-4;
}
}];
}
def GR16 : RegisterClass<"MSP430", [i16], 16,
// Volatile registers
[R12W, R13W, R14W, R15W, R11W, R10W, R9W, R8W, R7W, R6W, R5W,
// Frame pointer, sometimes allocable
FPW,
// Volatile, but not allocable
PCW, SPW, SRW, CGW]>
{
let SubRegClasses = [(GR8 subreg_8bit)];
let MethodProtos = [{
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
GR16Class::iterator
GR16Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetRegisterInfo *RI = TM.getRegisterInfo();
// Depending on whether the function uses frame pointer or not, last 5 or 4
// registers on the list above are reserved
if (RI->hasFP(MF))
return end()-5;
else
return end()-4;
}
}];
}