mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-17 18:10:31 +00:00
0d7952ed5a
same vt multiple times for a register. For example, ECX is in 5 different i32 reg classes, just return 1 i32 instead of 5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99727 91177308-0d34-0410-b5e6-96231b3b80d8
567 lines
20 KiB
C++
567 lines
20 KiB
C++
//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class wraps target description classes used by the various code
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// generation TableGen backends. This makes it easier to access the data and
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// provides a single place that needs to check it for validity. All of these
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// classes throw exceptions on error conditions.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "CodeGenIntrinsics.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include <algorithm>
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using namespace llvm;
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static cl::opt<unsigned>
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AsmParserNum("asmparsernum", cl::init(0),
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cl::desc("Make -gen-asm-parser emit assembly parser #N"));
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static cl::opt<unsigned>
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AsmWriterNum("asmwriternum", cl::init(0),
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cl::desc("Make -gen-asm-writer emit assembly writer #N"));
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/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
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/// record corresponds to.
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MVT::SimpleValueType llvm::getValueType(Record *Rec) {
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return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
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}
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std::string llvm::getName(MVT::SimpleValueType T) {
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switch (T) {
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case MVT::Other: return "UNKNOWN";
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case MVT::iPTR: return "TLI.getPointerTy()";
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case MVT::iPTRAny: return "TLI.getPointerTy()";
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default: return getEnumName(T);
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}
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}
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std::string llvm::getEnumName(MVT::SimpleValueType T) {
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switch (T) {
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case MVT::Other: return "MVT::Other";
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case MVT::i1: return "MVT::i1";
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case MVT::i8: return "MVT::i8";
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case MVT::i16: return "MVT::i16";
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case MVT::i32: return "MVT::i32";
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case MVT::i64: return "MVT::i64";
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case MVT::i128: return "MVT::i128";
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case MVT::iAny: return "MVT::iAny";
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case MVT::fAny: return "MVT::fAny";
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case MVT::vAny: return "MVT::vAny";
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case MVT::f32: return "MVT::f32";
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case MVT::f64: return "MVT::f64";
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case MVT::f80: return "MVT::f80";
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case MVT::f128: return "MVT::f128";
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case MVT::ppcf128: return "MVT::ppcf128";
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case MVT::Flag: return "MVT::Flag";
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case MVT::isVoid:return "MVT::isVoid";
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case MVT::v2i8: return "MVT::v2i8";
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case MVT::v4i8: return "MVT::v4i8";
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case MVT::v8i8: return "MVT::v8i8";
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case MVT::v16i8: return "MVT::v16i8";
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case MVT::v32i8: return "MVT::v32i8";
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case MVT::v2i16: return "MVT::v2i16";
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case MVT::v4i16: return "MVT::v4i16";
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case MVT::v8i16: return "MVT::v8i16";
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case MVT::v16i16: return "MVT::v16i16";
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case MVT::v2i32: return "MVT::v2i32";
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case MVT::v4i32: return "MVT::v4i32";
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case MVT::v8i32: return "MVT::v8i32";
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case MVT::v1i64: return "MVT::v1i64";
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case MVT::v2i64: return "MVT::v2i64";
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case MVT::v4i64: return "MVT::v4i64";
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case MVT::v2f32: return "MVT::v2f32";
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case MVT::v4f32: return "MVT::v4f32";
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case MVT::v8f32: return "MVT::v8f32";
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case MVT::v2f64: return "MVT::v2f64";
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case MVT::v4f64: return "MVT::v4f64";
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case MVT::Metadata: return "MVT::Metadata";
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case MVT::iPTR: return "MVT::iPTR";
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case MVT::iPTRAny: return "MVT::iPTRAny";
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default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
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}
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}
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/// getQualifiedName - Return the name of the specified record, with a
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/// namespace qualifier if the record contains one.
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///
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std::string llvm::getQualifiedName(const Record *R) {
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std::string Namespace = R->getValueAsString("Namespace");
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if (Namespace.empty()) return R->getName();
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return Namespace + "::" + R->getName();
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}
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/// getTarget - Return the current instance of the Target class.
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///
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CodeGenTarget::CodeGenTarget() {
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std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
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if (Targets.size() == 0)
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throw std::string("ERROR: No 'Target' subclasses defined!");
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if (Targets.size() != 1)
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throw std::string("ERROR: Multiple subclasses of Target defined!");
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TargetRec = Targets[0];
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}
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const std::string &CodeGenTarget::getName() const {
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return TargetRec->getName();
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}
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std::string CodeGenTarget::getInstNamespace() const {
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for (inst_iterator i = inst_begin(), e = inst_end(); i != e; ++i) {
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// Make sure not to pick up "TargetOpcode" by accidentally getting
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// the namespace off the PHI instruction or something.
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if ((*i)->Namespace != "TargetOpcode")
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return (*i)->Namespace;
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}
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return "";
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}
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Record *CodeGenTarget::getInstructionSet() const {
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return TargetRec->getValueAsDef("InstructionSet");
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}
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/// getAsmParser - Return the AssemblyParser definition for this target.
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///
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Record *CodeGenTarget::getAsmParser() const {
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std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
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if (AsmParserNum >= LI.size())
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throw "Target does not have an AsmParser #" + utostr(AsmParserNum) + "!";
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return LI[AsmParserNum];
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}
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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Record *CodeGenTarget::getAsmWriter() const {
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std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
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if (AsmWriterNum >= LI.size())
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throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
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return LI[AsmWriterNum];
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}
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void CodeGenTarget::ReadRegisters() const {
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std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
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if (Regs.empty())
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throw std::string("No 'Register' subclasses defined!");
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Registers.reserve(Regs.size());
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Registers.assign(Regs.begin(), Regs.end());
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}
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CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
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DeclaredSpillSize = R->getValueAsInt("SpillSize");
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DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
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}
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const std::string &CodeGenRegister::getName() const {
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return TheDef->getName();
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}
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void CodeGenTarget::ReadRegisterClasses() const {
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std::vector<Record*> RegClasses =
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Records.getAllDerivedDefinitions("RegisterClass");
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if (RegClasses.empty())
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throw std::string("No 'RegisterClass' subclasses defined!");
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RegisterClasses.reserve(RegClasses.size());
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RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
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}
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std::vector<MVT::SimpleValueType> CodeGenTarget::
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getRegisterVTs(Record *R) const {
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std::vector<MVT::SimpleValueType> Result;
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const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
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for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RegisterClasses[i];
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for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
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if (R == RC.Elements[ei]) {
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const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes();
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Result.insert(Result.end(), InVTs.begin(), InVTs.end());
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}
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}
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}
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// Remove duplicates.
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array_pod_sort(Result.begin(), Result.end());
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Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
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return Result;
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}
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CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
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// Rename anonymous register classes.
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if (R->getName().size() > 9 && R->getName()[9] == '.') {
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static unsigned AnonCounter = 0;
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R->setName("AnonRegClass_"+utostr(AnonCounter++));
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}
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std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
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for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
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Record *Type = TypeList[i];
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if (!Type->isSubClassOf("ValueType"))
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throw "RegTypes list member '" + Type->getName() +
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"' does not derive from the ValueType class!";
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VTs.push_back(getValueType(Type));
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}
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assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
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std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
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for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
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Record *Reg = RegList[i];
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if (!Reg->isSubClassOf("Register"))
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throw "Register Class member '" + Reg->getName() +
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"' does not derive from the Register class!";
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Elements.push_back(Reg);
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}
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std::vector<Record*> SubRegClassList =
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R->getValueAsListOfDefs("SubRegClassList");
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for (unsigned i = 0, e = SubRegClassList.size(); i != e; ++i) {
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Record *SubRegClass = SubRegClassList[i];
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if (!SubRegClass->isSubClassOf("RegisterClass"))
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throw "Register Class member '" + SubRegClass->getName() +
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"' does not derive from the RegisterClass class!";
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SubRegClasses.push_back(SubRegClass);
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}
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// Allow targets to override the size in bits of the RegisterClass.
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unsigned Size = R->getValueAsInt("Size");
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Namespace = R->getValueAsString("Namespace");
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SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
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SpillAlignment = R->getValueAsInt("Alignment");
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CopyCost = R->getValueAsInt("CopyCost");
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MethodBodies = R->getValueAsCode("MethodBodies");
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MethodProtos = R->getValueAsCode("MethodProtos");
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}
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const std::string &CodeGenRegisterClass::getName() const {
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return TheDef->getName();
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}
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void CodeGenTarget::ReadLegalValueTypes() const {
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const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
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for (unsigned i = 0, e = RCs.size(); i != e; ++i)
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for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri)
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LegalValueTypes.push_back(RCs[i].VTs[ri]);
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// Remove duplicates.
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std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
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LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
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LegalValueTypes.end()),
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LegalValueTypes.end());
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}
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void CodeGenTarget::ReadInstructions() const {
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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if (Insts.size() <= 2)
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throw std::string("No 'Instruction' subclasses defined!");
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// Parse the instructions defined in the .td file.
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std::string InstFormatName =
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getAsmWriter()->getValueAsString("InstFormatName");
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for (unsigned i = 0, e = Insts.size(); i != e; ++i) {
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std::string AsmStr = Insts[i]->getValueAsString(InstFormatName);
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Instructions[Insts[i]] = new CodeGenInstruction(Insts[i], AsmStr);
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}
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}
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static const CodeGenInstruction *
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GetInstByName(const char *Name,
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const DenseMap<const Record*, CodeGenInstruction*> &Insts) {
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const Record *Rec = Records.getDef(Name);
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DenseMap<const Record*, CodeGenInstruction*>::const_iterator
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I = Insts.find(Rec);
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if (Rec == 0 || I == Insts.end())
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throw std::string("Could not find '") + Name + "' instruction!";
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return I->second;
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}
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namespace {
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/// SortInstByName - Sorting predicate to sort instructions by name.
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///
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struct SortInstByName {
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bool operator()(const CodeGenInstruction *Rec1,
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const CodeGenInstruction *Rec2) const {
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return Rec1->TheDef->getName() < Rec2->TheDef->getName();
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}
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};
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}
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/// getInstructionsByEnumValue - Return all of the instructions defined by the
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/// target, ordered by their enum value.
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void CodeGenTarget::ComputeInstrsByEnum() const {
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const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions();
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const CodeGenInstruction *PHI = GetInstByName("PHI", Insts);
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const CodeGenInstruction *INLINEASM = GetInstByName("INLINEASM", Insts);
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const CodeGenInstruction *DBG_LABEL = GetInstByName("DBG_LABEL", Insts);
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const CodeGenInstruction *EH_LABEL = GetInstByName("EH_LABEL", Insts);
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const CodeGenInstruction *GC_LABEL = GetInstByName("GC_LABEL", Insts);
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const CodeGenInstruction *KILL = GetInstByName("KILL", Insts);
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const CodeGenInstruction *EXTRACT_SUBREG =
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GetInstByName("EXTRACT_SUBREG", Insts);
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const CodeGenInstruction *INSERT_SUBREG =
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GetInstByName("INSERT_SUBREG", Insts);
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const CodeGenInstruction *IMPLICIT_DEF = GetInstByName("IMPLICIT_DEF", Insts);
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const CodeGenInstruction *SUBREG_TO_REG =
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GetInstByName("SUBREG_TO_REG", Insts);
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const CodeGenInstruction *COPY_TO_REGCLASS =
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GetInstByName("COPY_TO_REGCLASS", Insts);
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const CodeGenInstruction *DBG_VALUE = GetInstByName("DBG_VALUE", Insts);
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// Print out the rest of the instructions now.
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InstrsByEnum.push_back(PHI);
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InstrsByEnum.push_back(INLINEASM);
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InstrsByEnum.push_back(DBG_LABEL);
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InstrsByEnum.push_back(EH_LABEL);
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InstrsByEnum.push_back(GC_LABEL);
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InstrsByEnum.push_back(KILL);
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InstrsByEnum.push_back(EXTRACT_SUBREG);
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InstrsByEnum.push_back(INSERT_SUBREG);
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InstrsByEnum.push_back(IMPLICIT_DEF);
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InstrsByEnum.push_back(SUBREG_TO_REG);
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InstrsByEnum.push_back(COPY_TO_REGCLASS);
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InstrsByEnum.push_back(DBG_VALUE);
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unsigned EndOfPredefines = InstrsByEnum.size();
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for (DenseMap<const Record*, CodeGenInstruction*>::const_iterator
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I = Insts.begin(), E = Insts.end(); I != E; ++I) {
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const CodeGenInstruction *CGI = I->second;
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if (CGI != PHI &&
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CGI != INLINEASM &&
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CGI != DBG_LABEL &&
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CGI != EH_LABEL &&
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CGI != GC_LABEL &&
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CGI != KILL &&
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CGI != EXTRACT_SUBREG &&
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CGI != INSERT_SUBREG &&
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CGI != IMPLICIT_DEF &&
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CGI != SUBREG_TO_REG &&
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CGI != COPY_TO_REGCLASS &&
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CGI != DBG_VALUE)
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InstrsByEnum.push_back(CGI);
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}
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// All of the instructions are now in random order based on the map iteration.
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// Sort them by name.
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std::sort(InstrsByEnum.begin()+EndOfPredefines, InstrsByEnum.end(),
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SortInstByName());
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}
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/// isLittleEndianEncoding - Return whether this target encodes its instruction
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/// in little-endian format, i.e. bits laid out in the order [0..n]
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///
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bool CodeGenTarget::isLittleEndianEncoding() const {
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return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
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}
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//===----------------------------------------------------------------------===//
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// ComplexPattern implementation
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//
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ComplexPattern::ComplexPattern(Record *R) {
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Ty = ::getValueType(R->getValueAsDef("Ty"));
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NumOperands = R->getValueAsInt("NumOperands");
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SelectFunc = R->getValueAsString("SelectFunc");
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RootNodes = R->getValueAsListOfDefs("RootNodes");
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// Parse the properties.
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Properties = 0;
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std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
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for (unsigned i = 0, e = PropList.size(); i != e; ++i)
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if (PropList[i]->getName() == "SDNPHasChain") {
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Properties |= 1 << SDNPHasChain;
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} else if (PropList[i]->getName() == "SDNPOptInFlag") {
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Properties |= 1 << SDNPOptInFlag;
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} else if (PropList[i]->getName() == "SDNPMayStore") {
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Properties |= 1 << SDNPMayStore;
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} else if (PropList[i]->getName() == "SDNPMayLoad") {
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Properties |= 1 << SDNPMayLoad;
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} else if (PropList[i]->getName() == "SDNPSideEffect") {
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Properties |= 1 << SDNPSideEffect;
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} else if (PropList[i]->getName() == "SDNPMemOperand") {
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Properties |= 1 << SDNPMemOperand;
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} else if (PropList[i]->getName() == "SDNPVariadic") {
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Properties |= 1 << SDNPVariadic;
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} else {
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errs() << "Unsupported SD Node property '" << PropList[i]->getName()
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<< "' on ComplexPattern '" << R->getName() << "'!\n";
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exit(1);
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}
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}
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//===----------------------------------------------------------------------===//
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// CodeGenIntrinsic Implementation
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//===----------------------------------------------------------------------===//
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std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC,
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bool TargetOnly) {
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std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
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std::vector<CodeGenIntrinsic> Result;
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for (unsigned i = 0, e = I.size(); i != e; ++i) {
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bool isTarget = I[i]->getValueAsBit("isTarget");
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if (isTarget == TargetOnly)
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Result.push_back(CodeGenIntrinsic(I[i]));
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}
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return Result;
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}
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CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
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TheDef = R;
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std::string DefName = R->getName();
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ModRef = WriteMem;
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isOverloaded = false;
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isCommutative = false;
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if (DefName.size() <= 4 ||
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std::string(DefName.begin(), DefName.begin() + 4) != "int_")
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throw "Intrinsic '" + DefName + "' does not start with 'int_'!";
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EnumName = std::string(DefName.begin()+4, DefName.end());
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if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
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GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
|
|
|
|
TargetPrefix = R->getValueAsString("TargetPrefix");
|
|
Name = R->getValueAsString("LLVMName");
|
|
|
|
if (Name == "") {
|
|
// If an explicit name isn't specified, derive one from the DefName.
|
|
Name = "llvm.";
|
|
|
|
for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
|
|
Name += (EnumName[i] == '_') ? '.' : EnumName[i];
|
|
} else {
|
|
// Verify it starts with "llvm.".
|
|
if (Name.size() <= 5 ||
|
|
std::string(Name.begin(), Name.begin() + 5) != "llvm.")
|
|
throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!";
|
|
}
|
|
|
|
// If TargetPrefix is specified, make sure that Name starts with
|
|
// "llvm.<targetprefix>.".
|
|
if (!TargetPrefix.empty()) {
|
|
if (Name.size() < 6+TargetPrefix.size() ||
|
|
std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
|
|
!= (TargetPrefix + "."))
|
|
throw "Intrinsic '" + DefName + "' does not start with 'llvm." +
|
|
TargetPrefix + ".'!";
|
|
}
|
|
|
|
// Parse the list of return types.
|
|
std::vector<MVT::SimpleValueType> OverloadedVTs;
|
|
ListInit *TypeList = R->getValueAsListInit("RetTypes");
|
|
for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
|
|
Record *TyEl = TypeList->getElementAsRecord(i);
|
|
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
|
|
MVT::SimpleValueType VT;
|
|
if (TyEl->isSubClassOf("LLVMMatchType")) {
|
|
unsigned MatchTy = TyEl->getValueAsInt("Number");
|
|
assert(MatchTy < OverloadedVTs.size() &&
|
|
"Invalid matching number!");
|
|
VT = OverloadedVTs[MatchTy];
|
|
// It only makes sense to use the extended and truncated vector element
|
|
// variants with iAny types; otherwise, if the intrinsic is not
|
|
// overloaded, all the types can be specified directly.
|
|
assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") &&
|
|
!TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) ||
|
|
VT == MVT::iAny || VT == MVT::vAny) &&
|
|
"Expected iAny or vAny type");
|
|
} else {
|
|
VT = getValueType(TyEl->getValueAsDef("VT"));
|
|
}
|
|
if (EVT(VT).isOverloaded()) {
|
|
OverloadedVTs.push_back(VT);
|
|
isOverloaded = true;
|
|
}
|
|
|
|
// Reject invalid types.
|
|
if (VT == MVT::isVoid)
|
|
throw "Intrinsic '" + DefName + " has void in result type list!";
|
|
|
|
IS.RetVTs.push_back(VT);
|
|
IS.RetTypeDefs.push_back(TyEl);
|
|
}
|
|
|
|
// Parse the list of parameter types.
|
|
TypeList = R->getValueAsListInit("ParamTypes");
|
|
for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
|
|
Record *TyEl = TypeList->getElementAsRecord(i);
|
|
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
|
|
MVT::SimpleValueType VT;
|
|
if (TyEl->isSubClassOf("LLVMMatchType")) {
|
|
unsigned MatchTy = TyEl->getValueAsInt("Number");
|
|
assert(MatchTy < OverloadedVTs.size() &&
|
|
"Invalid matching number!");
|
|
VT = OverloadedVTs[MatchTy];
|
|
// It only makes sense to use the extended and truncated vector element
|
|
// variants with iAny types; otherwise, if the intrinsic is not
|
|
// overloaded, all the types can be specified directly.
|
|
assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") &&
|
|
!TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) ||
|
|
VT == MVT::iAny || VT == MVT::vAny) &&
|
|
"Expected iAny or vAny type");
|
|
} else
|
|
VT = getValueType(TyEl->getValueAsDef("VT"));
|
|
|
|
if (EVT(VT).isOverloaded()) {
|
|
OverloadedVTs.push_back(VT);
|
|
isOverloaded = true;
|
|
}
|
|
|
|
// Reject invalid types.
|
|
if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
|
|
throw "Intrinsic '" + DefName + " has void in result type list!";
|
|
|
|
IS.ParamVTs.push_back(VT);
|
|
IS.ParamTypeDefs.push_back(TyEl);
|
|
}
|
|
|
|
// Parse the intrinsic properties.
|
|
ListInit *PropList = R->getValueAsListInit("Properties");
|
|
for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) {
|
|
Record *Property = PropList->getElementAsRecord(i);
|
|
assert(Property->isSubClassOf("IntrinsicProperty") &&
|
|
"Expected a property!");
|
|
|
|
if (Property->getName() == "IntrNoMem")
|
|
ModRef = NoMem;
|
|
else if (Property->getName() == "IntrReadArgMem")
|
|
ModRef = ReadArgMem;
|
|
else if (Property->getName() == "IntrReadMem")
|
|
ModRef = ReadMem;
|
|
else if (Property->getName() == "IntrWriteArgMem")
|
|
ModRef = WriteArgMem;
|
|
else if (Property->getName() == "IntrWriteMem")
|
|
ModRef = WriteMem;
|
|
else if (Property->getName() == "Commutative")
|
|
isCommutative = true;
|
|
else if (Property->isSubClassOf("NoCapture")) {
|
|
unsigned ArgNo = Property->getValueAsInt("ArgNo");
|
|
ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
|
|
} else
|
|
assert(0 && "Unknown property!");
|
|
}
|
|
}
|