llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-23 20:29:30 +00:00

History

Chandler Carruth cad1711154 [x86] Begin stubbing out the AVX support in the new vector shuffle

lowering scheme.

Currently, this just directly bails to the fallback path of splitting
the 256-bit vector into two 128-bit vectors, operating there, and then
joining the results back together. While the results are far from
perfect, they are *shockingly* good for what we're doing here. I'll be
layering the rest of the functionality on top of this piece by piece and
updating tests as I go.

Note that 256-bit vectors in this mode are still somewhat WIP. While
I think the code paths that I'm adding here are clean and good-to-go,
there are still a lot of 128-bit assumptions that I'll need to stomp out
as I march through the functional spread here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215637 91177308-0d34-0410-b5e6-96231b3b80d8

2014-08-14 12:13:59 +00:00

Analysis

In LVI(Lazy Value Info), originally value on a BB can only be caculated once,

2014-08-11 05:02:04 +00:00

AsmParser

Canonicalize header guards into a common format.

2014-08-13 16:26:38 +00:00

Bitcode

Canonicalize header guards into a common format.

2014-08-13 16:26:38 +00:00

CodeGen

[SDAG] Fix a bug in the DAG combiner where we would fail to return the