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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
142 lines
4.3 KiB
C++
142 lines
4.3 KiB
C++
//===-- NEONMoveFix.cpp - Convert vfp reg-reg moves into neon ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "neon-mov-fix"
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#include "ARM.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMInstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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STATISTIC(NumVMovs, "Number of reg-reg moves converted");
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namespace {
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struct NEONMoveFixPass : public MachineFunctionPass {
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static char ID;
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NEONMoveFixPass() : MachineFunctionPass(ID) {}
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual const char *getPassName() const {
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return "NEON reg-reg move conversion";
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}
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private:
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const TargetRegisterInfo *TRI;
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const ARMBaseInstrInfo *TII;
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typedef DenseMap<unsigned, const MachineInstr*> RegMap;
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bool InsertMoves(MachineBasicBlock &MBB);
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};
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char NEONMoveFixPass::ID = 0;
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}
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bool NEONMoveFixPass::InsertMoves(MachineBasicBlock &MBB) {
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RegMap Defs;
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bool Modified = false;
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// Walk over MBB tracking the def points of the registers.
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MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
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MachineBasicBlock::iterator NextMII;
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for (; MII != E; MII = NextMII) {
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NextMII = llvm::next(MII);
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MachineInstr *MI = &*MII;
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if (MI->getOpcode() == ARM::VMOVD &&
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!TII->isPredicated(MI)) {
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unsigned SrcReg = MI->getOperand(1).getReg();
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// If we do not find an instruction defining the reg, this means the
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// register should be live-in for this BB. It's always to better to use
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// NEON reg-reg moves.
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unsigned Domain = ARMII::DomainNEON;
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RegMap::iterator DefMI = Defs.find(SrcReg);
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if (DefMI != Defs.end()) {
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Domain = DefMI->second->getDesc().TSFlags & ARMII::DomainMask;
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// Instructions in general domain are subreg accesses.
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// Map them to NEON reg-reg moves.
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if (Domain == ARMII::DomainGeneral)
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Domain = ARMII::DomainNEON;
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}
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if (Domain & ARMII::DomainNEON) {
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// Convert VMOVD to VMOVDneon
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unsigned DestReg = MI->getOperand(0).getReg();
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DEBUG({errs() << "vmov convert: "; MI->dump();});
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// It's safe to ignore imp-defs / imp-uses here, since:
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// - We're running late, no intelligent condegen passes should be run
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// afterwards
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// - The imp-defs / imp-uses are superregs only, we don't care about
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// them.
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AddDefaultPred(BuildMI(MBB, *MI, MI->getDebugLoc(),
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TII->get(ARM::VMOVDneon), DestReg).addReg(SrcReg));
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MBB.erase(MI);
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MachineBasicBlock::iterator I = prior(NextMII);
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MI = &*I;
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DEBUG({errs() << " into: "; MI->dump();});
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Modified = true;
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++NumVMovs;
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} else {
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assert((Domain & ARMII::DomainVFP) && "Invalid domain!");
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// Do nothing.
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}
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}
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// Update def information.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand& MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef())
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continue;
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unsigned MOReg = MO.getReg();
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Defs[MOReg] = MI;
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// Catch aliases as well.
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for (const unsigned *R = TRI->getAliasSet(MOReg); *R; ++R)
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Defs[*R] = MI;
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}
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}
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return Modified;
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}
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bool NEONMoveFixPass::runOnMachineFunction(MachineFunction &Fn) {
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ARMFunctionInfo *AFI = Fn.getInfo<ARMFunctionInfo>();
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const TargetMachine &TM = Fn.getTarget();
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if (AFI->isThumb1OnlyFunction())
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return false;
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TRI = TM.getRegisterInfo();
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TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
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bool Modified = false;
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for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
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++MFI) {
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MachineBasicBlock &MBB = *MFI;
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Modified |= InsertMoves(MBB);
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}
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return Modified;
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}
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/// createNEONMoveFixPass - Returns an instance of the NEON reg-reg moves fix
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/// pass.
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FunctionPass *llvm::createNEONMoveFixPass() {
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return new NEONMoveFixPass();
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}
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