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Teach vector legalization how to honor Promote for int to float conversions. The code checking whether to promote the operation knew to look at the operand, but the actual promotion code didn't. This fixes that. The operand is promoted up via [zs]ext. rdar://11762659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159378 91177308-0d34-0410-b5e6-96231b3b80d8
552 lines
20 KiB
C++
552 lines
20 KiB
C++
//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SelectionDAG::LegalizeVectors method.
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//
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// The vector legalizer looks for vector operations which might need to be
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// scalarized and legalizes them. This is a separate step from Legalize because
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// scalarizing can introduce illegal types. For example, suppose we have an
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// ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
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// on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
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// operation, which introduces nodes with the illegal type i64 which must be
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// expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
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// the operation must be unrolled, which introduces nodes with the illegal
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// type i8 which must be promoted.
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//
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// This does not legalize vector manipulations like ISD::BUILD_VECTOR,
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// or operations that happen to take a vector which are custom-lowered;
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// the legalization for such operations never produces nodes
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// with illegal types, so it's okay to put off legalizing them until
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// SelectionDAG::Legalize runs.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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namespace {
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class VectorLegalizer {
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SelectionDAG& DAG;
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const TargetLowering &TLI;
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bool Changed; // Keep track of whether anything changed
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/// LegalizedNodes - For nodes that are of legal width, and that have more
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/// than one use, this map indicates what regularized operand to use. This
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/// allows us to avoid legalizing the same thing more than once.
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DenseMap<SDValue, SDValue> LegalizedNodes;
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// Adds a node to the translation cache
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void AddLegalizedOperand(SDValue From, SDValue To) {
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LegalizedNodes.insert(std::make_pair(From, To));
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// If someone requests legalization of the new node, return itself.
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if (From != To)
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LegalizedNodes.insert(std::make_pair(To, To));
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}
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// Legalizes the given node
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SDValue LegalizeOp(SDValue Op);
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// Assuming the node is legal, "legalize" the results
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SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
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// Implements unrolling a VSETCC.
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SDValue UnrollVSETCC(SDValue Op);
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// Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB
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// isn't legal.
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// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
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// SINT_TO_FLOAT and SHR on vectors isn't legal.
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SDValue ExpandUINT_TO_FLOAT(SDValue Op);
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// Implement vselect in terms of XOR, AND, OR when blend is not supported
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// by the target.
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SDValue ExpandVSELECT(SDValue Op);
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SDValue ExpandLoad(SDValue Op);
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SDValue ExpandStore(SDValue Op);
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SDValue ExpandFNEG(SDValue Op);
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// Implements vector promotion; this is essentially just bitcasting the
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// operands to a different type and bitcasting the result back to the
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// original type.
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SDValue PromoteVectorOp(SDValue Op);
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// Implements [SU]INT_TO_FP vector promotion; this is a [zs]ext of the input
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// operand to the next size up.
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SDValue PromoteVectorOpINT_TO_FP(SDValue Op);
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public:
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bool Run();
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VectorLegalizer(SelectionDAG& dag) :
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DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
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};
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bool VectorLegalizer::Run() {
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// The legalize process is inherently a bottom-up recursive process (users
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// legalize their uses before themselves). Given infinite stack space, we
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// could just start legalizing on the root and traverse the whole graph. In
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// practice however, this causes us to run out of stack space on large basic
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// blocks. To avoid this problem, compute an ordering of the nodes where each
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// node is only legalized after all of its operands are legalized.
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DAG.AssignTopologicalOrder();
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for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
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E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
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LegalizeOp(SDValue(I, 0));
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// Finally, it's possible the root changed. Get the new root.
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SDValue OldRoot = DAG.getRoot();
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assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
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DAG.setRoot(LegalizedNodes[OldRoot]);
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LegalizedNodes.clear();
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// Remove dead nodes now.
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DAG.RemoveDeadNodes();
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return Changed;
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}
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SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
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// Generic legalization: just pass the operand through.
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for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
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AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
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return Result.getValue(Op.getResNo());
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}
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SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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// Note that LegalizeOp may be reentered even from single-use nodes, which
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// means that we always must cache transformed nodes.
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DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
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if (I != LegalizedNodes.end()) return I->second;
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SDNode* Node = Op.getNode();
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// Legalize the operands
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SmallVector<SDValue, 8> Ops;
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for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
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Ops.push_back(LegalizeOp(Node->getOperand(i)));
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SDValue Result =
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SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0);
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if (Op.getOpcode() == ISD::LOAD) {
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LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
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if (TLI.isLoadExtLegal(LD->getExtensionType(), LD->getMemoryVT()))
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return TranslateLegalizeResults(Op, Result);
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Changed = true;
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return LegalizeOp(ExpandLoad(Op));
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}
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} else if (Op.getOpcode() == ISD::STORE) {
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StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
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EVT StVT = ST->getMemoryVT();
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EVT ValVT = ST->getValue().getValueType();
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if (StVT.isVector() && ST->isTruncatingStore())
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switch (TLI.getTruncStoreAction(ValVT, StVT)) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Legal:
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return TranslateLegalizeResults(Op, Result);
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case TargetLowering::Custom:
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Changed = true;
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return LegalizeOp(TLI.LowerOperation(Result, DAG));
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case TargetLowering::Expand:
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Changed = true;
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return LegalizeOp(ExpandStore(Op));
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}
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}
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bool HasVectorValue = false;
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for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
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J != E;
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++J)
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HasVectorValue |= J->isVector();
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if (!HasVectorValue)
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return TranslateLegalizeResults(Op, Result);
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EVT QueryType;
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switch (Op.getOpcode()) {
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default:
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return TranslateLegalizeResults(Op, Result);
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case ISD::ADD:
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case ISD::SUB:
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case ISD::MUL:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SREM:
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case ISD::UREM:
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::FDIV:
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case ISD::FREM:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRL:
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case ISD::ROTL:
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case ISD::ROTR:
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case ISD::CTLZ:
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case ISD::CTTZ:
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case ISD::CTLZ_ZERO_UNDEF:
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case ISD::CTTZ_ZERO_UNDEF:
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case ISD::CTPOP:
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case ISD::SELECT:
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case ISD::VSELECT:
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case ISD::SELECT_CC:
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case ISD::SETCC:
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case ISD::ZERO_EXTEND:
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case ISD::ANY_EXTEND:
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case ISD::TRUNCATE:
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case ISD::SIGN_EXTEND:
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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case ISD::FNEG:
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case ISD::FABS:
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FPOWI:
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case ISD::FPOW:
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FCEIL:
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case ISD::FTRUNC:
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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case ISD::FFLOOR:
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case ISD::SIGN_EXTEND_INREG:
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QueryType = Node->getValueType(0);
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break;
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case ISD::FP_ROUND_INREG:
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QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
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break;
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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QueryType = Node->getOperand(0).getValueType();
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break;
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}
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switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
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case TargetLowering::Promote:
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switch (Op.getOpcode()) {
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default:
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// "Promote" the operation by bitcasting
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Result = PromoteVectorOp(Op);
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Changed = true;
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break;
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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// "Promote" the operation by extending the operand.
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Result = PromoteVectorOpINT_TO_FP(Op);
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Changed = true;
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break;
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}
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break;
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case TargetLowering::Legal: break;
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case TargetLowering::Custom: {
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SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
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if (Tmp1.getNode()) {
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Result = Tmp1;
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break;
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}
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// FALL THROUGH
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}
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case TargetLowering::Expand:
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if (Node->getOpcode() == ISD::VSELECT)
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Result = ExpandVSELECT(Op);
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else if (Node->getOpcode() == ISD::UINT_TO_FP)
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Result = ExpandUINT_TO_FLOAT(Op);
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else if (Node->getOpcode() == ISD::FNEG)
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Result = ExpandFNEG(Op);
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else if (Node->getOpcode() == ISD::SETCC)
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Result = UnrollVSETCC(Op);
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else
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Result = DAG.UnrollVectorOp(Op.getNode());
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break;
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}
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// Make sure that the generated code is itself legal.
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if (Result != Op) {
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Result = LegalizeOp(Result);
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Changed = true;
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}
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// Note that LegalizeOp may be reentered even from single-use nodes, which
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// means that we always must cache transformed nodes.
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AddLegalizedOperand(Op, Result);
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return Result;
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}
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SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
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// Vector "promotion" is basically just bitcasting and doing the operation
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// in a different type. For example, x86 promotes ISD::AND on v2i32 to
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// v1i64.
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EVT VT = Op.getValueType();
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assert(Op.getNode()->getNumValues() == 1 &&
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"Can't promote a vector with multiple results!");
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EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
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DebugLoc dl = Op.getDebugLoc();
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SmallVector<SDValue, 4> Operands(Op.getNumOperands());
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for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
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if (Op.getOperand(j).getValueType().isVector())
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Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
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else
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Operands[j] = Op.getOperand(j);
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}
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Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size());
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return DAG.getNode(ISD::BITCAST, dl, VT, Op);
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}
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SDValue VectorLegalizer::PromoteVectorOpINT_TO_FP(SDValue Op) {
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// INT_TO_FP operations may require the input operand be promoted even
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// when the type is otherwise legal.
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EVT VT = Op.getOperand(0).getValueType();
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assert(Op.getNode()->getNumValues() == 1 &&
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"Can't promote a vector with multiple results!");
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// Normal getTypeToPromoteTo() doesn't work here, as that will promote
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// by widening the vector w/ the same element width and twice the number
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// of elements. We want the other way around, the same number of elements,
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// each twice the width.
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//
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// Increase the bitwidth of the element to the next pow-of-two
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// (which is greater than 8 bits).
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unsigned NumElts = VT.getVectorNumElements();
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EVT EltVT = VT.getVectorElementType();
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EltVT = EVT::getIntegerVT(*DAG.getContext(), 2 * EltVT.getSizeInBits());
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assert(EltVT.isSimple() && "Promoting to a non-simple vector type!");
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// Build a new vector type and check if it is legal.
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MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
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DebugLoc dl = Op.getDebugLoc();
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SmallVector<SDValue, 4> Operands(Op.getNumOperands());
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unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
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ISD::SIGN_EXTEND;
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for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
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if (Op.getOperand(j).getValueType().isVector())
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Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
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else
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Operands[j] = Op.getOperand(j);
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}
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return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), &Operands[0],
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Operands.size());
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}
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SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
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DebugLoc dl = Op.getDebugLoc();
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LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
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SDValue Chain = LD->getChain();
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SDValue BasePTR = LD->getBasePtr();
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EVT SrcVT = LD->getMemoryVT();
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ISD::LoadExtType ExtType = LD->getExtensionType();
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SmallVector<SDValue, 8> LoadVals;
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SmallVector<SDValue, 8> LoadChains;
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unsigned NumElem = SrcVT.getVectorNumElements();
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unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
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for (unsigned Idx=0; Idx<NumElem; Idx++) {
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SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
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Op.getNode()->getValueType(0).getScalarType(),
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Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
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SrcVT.getScalarType(),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->getAlignment());
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BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
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DAG.getIntPtrConstant(Stride));
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LoadVals.push_back(ScalarLoad.getValue(0));
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LoadChains.push_back(ScalarLoad.getValue(1));
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}
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SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&LoadChains[0], LoadChains.size());
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SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
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Op.getNode()->getValueType(0), &LoadVals[0], LoadVals.size());
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AddLegalizedOperand(Op.getValue(0), Value);
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AddLegalizedOperand(Op.getValue(1), NewChain);
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return (Op.getResNo() ? NewChain : Value);
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}
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SDValue VectorLegalizer::ExpandStore(SDValue Op) {
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DebugLoc dl = Op.getDebugLoc();
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StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
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SDValue Chain = ST->getChain();
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SDValue BasePTR = ST->getBasePtr();
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SDValue Value = ST->getValue();
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EVT StVT = ST->getMemoryVT();
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unsigned Alignment = ST->getAlignment();
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bool isVolatile = ST->isVolatile();
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bool isNonTemporal = ST->isNonTemporal();
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unsigned NumElem = StVT.getVectorNumElements();
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// The type of the data we want to save
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EVT RegVT = Value.getValueType();
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EVT RegSclVT = RegVT.getScalarType();
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// The type of data as saved in memory.
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EVT MemSclVT = StVT.getScalarType();
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// Cast floats into integers
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unsigned ScalarSize = MemSclVT.getSizeInBits();
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// Round odd types to the next pow of two.
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if (!isPowerOf2_32(ScalarSize))
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ScalarSize = NextPowerOf2(ScalarSize);
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// Store Stride in bytes
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unsigned Stride = ScalarSize/8;
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// Extract each of the elements from the original vector
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// and save them into memory individually.
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SmallVector<SDValue, 8> Stores;
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for (unsigned Idx = 0; Idx < NumElem; Idx++) {
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SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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RegSclVT, Value, DAG.getIntPtrConstant(Idx));
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// This scalar TruncStore may be illegal, but we legalize it later.
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SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
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ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
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isVolatile, isNonTemporal, Alignment);
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BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
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DAG.getIntPtrConstant(Stride));
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Stores.push_back(Store);
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}
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SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&Stores[0], Stores.size());
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AddLegalizedOperand(Op, TF);
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return TF;
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}
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SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
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// Implement VSELECT in terms of XOR, AND, OR
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// on platforms which do not support blend natively.
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EVT VT = Op.getOperand(0).getValueType();
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DebugLoc DL = Op.getDebugLoc();
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SDValue Mask = Op.getOperand(0);
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SDValue Op1 = Op.getOperand(1);
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SDValue Op2 = Op.getOperand(2);
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// If we can't even use the basic vector operations of
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// AND,OR,XOR, we will have to scalarize the op.
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// Notice that the operation may be 'promoted' which means that it is
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// 'bitcasted' to another type which is handled.
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if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
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|
TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
|
|
TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand)
|
|
return DAG.UnrollVectorOp(Op.getNode());
|
|
|
|
assert(VT.getSizeInBits() == Op.getOperand(1).getValueType().getSizeInBits()
|
|
&& "Invalid mask size");
|
|
// Bitcast the operands to be the same type as the mask.
|
|
// This is needed when we select between FP types because
|
|
// the mask is a vector of integers.
|
|
Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
|
|
Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
|
|
|
|
SDValue AllOnes = DAG.getConstant(
|
|
APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT);
|
|
SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
|
|
|
|
Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
|
|
Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
|
|
SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
|
|
return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
|
|
}
|
|
|
|
SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
|
|
EVT VT = Op.getOperand(0).getValueType();
|
|
DebugLoc DL = Op.getDebugLoc();
|
|
|
|
// Make sure that the SINT_TO_FP and SRL instructions are available.
|
|
if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
|
|
TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
|
|
return DAG.UnrollVectorOp(Op.getNode());
|
|
|
|
EVT SVT = VT.getScalarType();
|
|
assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
|
|
"Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
|
|
|
|
unsigned BW = SVT.getSizeInBits();
|
|
SDValue HalfWord = DAG.getConstant(BW/2, VT);
|
|
|
|
// Constants to clear the upper part of the word.
|
|
// Notice that we can also use SHL+SHR, but using a constant is slightly
|
|
// faster on x86.
|
|
uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
|
|
SDValue HalfWordMask = DAG.getConstant(HWMask, VT);
|
|
|
|
// Two to the power of half-word-size.
|
|
SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType());
|
|
|
|
// Clear upper part of LO, lower HI
|
|
SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
|
|
SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
|
|
|
|
// Convert hi and lo to floats
|
|
// Convert the hi part back to the upper values
|
|
SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
|
|
fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
|
|
SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
|
|
|
|
// Add the two halves
|
|
return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
|
|
}
|
|
|
|
|
|
SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
|
|
if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
|
|
SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
|
|
return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
|
|
Zero, Op.getOperand(0));
|
|
}
|
|
return DAG.UnrollVectorOp(Op.getNode());
|
|
}
|
|
|
|
SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
|
|
EVT VT = Op.getValueType();
|
|
unsigned NumElems = VT.getVectorNumElements();
|
|
EVT EltVT = VT.getVectorElementType();
|
|
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
|
|
EVT TmpEltVT = LHS.getValueType().getVectorElementType();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
SmallVector<SDValue, 8> Ops(NumElems);
|
|
for (unsigned i = 0; i < NumElems; ++i) {
|
|
SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
|
|
DAG.getIntPtrConstant(i));
|
|
SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
|
|
DAG.getIntPtrConstant(i));
|
|
Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
|
|
LHSElem, RHSElem, CC);
|
|
Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i],
|
|
DAG.getConstant(APInt::getAllOnesValue
|
|
(EltVT.getSizeInBits()), EltVT),
|
|
DAG.getConstant(0, EltVT));
|
|
}
|
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
|
|
}
|
|
|
|
}
|
|
|
|
bool SelectionDAG::LegalizeVectors() {
|
|
return VectorLegalizer(*this).Run();
|
|
}
|