mirror of
https://github.com/c64scene-ar/llvm-6502.git
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36a9b31b98
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
1396 lines
65 KiB
TableGen
1396 lines
65 KiB
TableGen
//===-- X86InstrArithmetic.td - Integer Arithmetic Instrs --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the integer arithmetic instructions in the X86
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// architecture.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// LEA - Load Effective Address
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let SchedRW = [WriteLEA] in {
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let neverHasSideEffects = 1 in
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def LEA16r : I<0x8D, MRMSrcMem,
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(outs GR16:$dst), (ins i32mem:$src),
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"lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize;
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let isReMaterializable = 1 in
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def LEA32r : I<0x8D, MRMSrcMem,
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(outs GR32:$dst), (ins i32mem:$src),
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"lea{l}\t{$src|$dst}, {$dst|$src}",
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[(set GR32:$dst, lea32addr:$src)], IIC_LEA>,
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Requires<[In32BitMode]>;
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def LEA64_32r : I<0x8D, MRMSrcMem,
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(outs GR32:$dst), (ins lea64_32mem:$src),
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"lea{l}\t{$src|$dst}, {$dst|$src}",
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[(set GR32:$dst, lea64_32addr:$src)], IIC_LEA>,
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Requires<[In64BitMode]>;
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let isReMaterializable = 1 in
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def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
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"lea{q}\t{$src|$dst}, {$dst|$src}",
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[(set GR64:$dst, lea64addr:$src)], IIC_LEA>;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Fixed-Register Multiplication and Division Instructions.
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//
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// SchedModel info for instruction that loads one value and gets the second
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// (and possibly third) value from a register.
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// This is used for instructions that put the memory operands before other
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// uses.
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class SchedLoadReg<SchedWrite SW> : Sched<[SW,
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// Memory operand.
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ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
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// Register reads (implicit or explicit).
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ReadAfterLd, ReadAfterLd]>;
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// Extra precision multiplication
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// AL is really implied by AX, but the registers in Defs must match the
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// SDNode results (i8, i32).
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// AL,AH = AL*GR8
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let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
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// FIXME: Used for 8-bit mul, ignore result upper 8 bits.
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// This probably ought to be moved to a def : Pat<> if the
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// syntax can be accepted.
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[(set AL, (mul AL, GR8:$src)),
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(implicit EFLAGS)], IIC_MUL8>, Sched<[WriteIMul]>;
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// AX,DX = AX*GR16
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let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
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def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
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"mul{w}\t$src",
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[], IIC_MUL16_REG>, OpSize, Sched<[WriteIMul]>;
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// EAX,EDX = EAX*GR32
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
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def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
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"mul{l}\t$src",
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[/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],
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IIC_MUL32_REG>, Sched<[WriteIMul]>;
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// RAX,RDX = RAX*GR64
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
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def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
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"mul{q}\t$src",
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[/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
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IIC_MUL64>, Sched<[WriteIMul]>;
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// AL,AH = AL*[mem8]
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let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
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"mul{b}\t$src",
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// FIXME: Used for 8-bit mul, ignore result upper 8 bits.
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// This probably ought to be moved to a def : Pat<> if the
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// syntax can be accepted.
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[(set AL, (mul AL, (loadi8 addr:$src))),
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(implicit EFLAGS)], IIC_MUL8>, SchedLoadReg<WriteIMulLd>;
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// AX,DX = AX*[mem16]
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let mayLoad = 1, neverHasSideEffects = 1 in {
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
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"mul{w}\t$src",
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[], IIC_MUL16_MEM>, OpSize, SchedLoadReg<WriteIMulLd>;
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// EAX,EDX = EAX*[mem32]
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
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"mul{l}\t$src",
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[], IIC_MUL32_MEM>, SchedLoadReg<WriteIMulLd>;
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// RAX,RDX = RAX*[mem64]
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
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"mul{q}\t$src", [], IIC_MUL64>, SchedLoadReg<WriteIMulLd>;
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}
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let neverHasSideEffects = 1 in {
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// AL,AH = AL*GR8
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let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [],
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IIC_IMUL8>, Sched<[WriteIMul]>;
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// AX,DX = AX*GR16
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [],
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IIC_IMUL16_RR>, OpSize, Sched<[WriteIMul]>;
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// EAX,EDX = EAX*GR32
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],
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IIC_IMUL32_RR>, Sched<[WriteIMul]>;
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// RAX,RDX = RAX*GR64
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],
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IIC_IMUL64_RR>, Sched<[WriteIMul]>;
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let mayLoad = 1 in {
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// AL,AH = AL*[mem8]
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let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
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"imul{b}\t$src", [], IIC_IMUL8>, SchedLoadReg<WriteIMulLd>;
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// AX,DX = AX*[mem16]
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
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"imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize,
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SchedLoadReg<WriteIMulLd>;
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// EAX,EDX = EAX*[mem32]
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
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"imul{l}\t$src", [], IIC_IMUL32_MEM>, SchedLoadReg<WriteIMulLd>;
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// RAX,RDX = RAX*[mem64]
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
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"imul{q}\t$src", [], IIC_IMUL64>, SchedLoadReg<WriteIMulLd>;
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}
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} // neverHasSideEffects
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let Defs = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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let isCommutable = 1, SchedRW = [WriteIMul] in {
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// X = IMUL Y, Z --> X = IMUL Z, Y
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// Register-Register Signed Integer Multiply
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def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
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"imul{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag GR16:$src1, GR16:$src2))], IIC_IMUL16_RR>,
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TB, OpSize;
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def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
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"imul{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>,
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TB;
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def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"imul{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, GR64:$src2))], IIC_IMUL64_RR>,
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TB;
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} // isCommutable, SchedRW
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// Register-Memory Signed Integer Multiply
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let SchedRW = [WriteIMulLd, ReadAfterLd] in {
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def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
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(ins GR16:$src1, i16mem:$src2),
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"imul{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag GR16:$src1, (load addr:$src2)))],
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IIC_IMUL16_RM>,
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TB, OpSize;
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def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
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(ins GR32:$src1, i32mem:$src2),
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"imul{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, (load addr:$src2)))],
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IIC_IMUL32_RM>,
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TB;
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def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
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(ins GR64:$src1, i64mem:$src2),
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"imul{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, (load addr:$src2)))],
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IIC_IMUL64_RM>,
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TB;
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} // SchedRW
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} // Constraints = "$src1 = $dst"
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} // Defs = [EFLAGS]
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// Surprisingly enough, these are not two address instructions!
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let Defs = [EFLAGS] in {
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let SchedRW = [WriteIMul] in {
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// Register-Integer Signed Integer Multiply
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def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
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(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag GR16:$src1, imm:$src2))],
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IIC_IMUL16_RRI>, OpSize;
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def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
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(outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
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"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag GR16:$src1, i16immSExt8:$src2))],
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IIC_IMUL16_RRI>,
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OpSize;
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def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
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(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, imm:$src2))],
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IIC_IMUL32_RRI>;
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def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
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(outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
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"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, i32immSExt8:$src2))],
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IIC_IMUL32_RRI>;
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def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
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(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, i64immSExt32:$src2))],
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IIC_IMUL64_RRI>;
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def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
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(outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag GR64:$src1, i64immSExt8:$src2))],
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IIC_IMUL64_RRI>;
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} // SchedRW
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// Memory-Integer Signed Integer Multiply
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let SchedRW = [WriteIMulLd] in {
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def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
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(outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
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"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1), imm:$src2))],
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IIC_IMUL16_RMI>,
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OpSize;
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def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
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(outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
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"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1),
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i16immSExt8:$src2))], IIC_IMUL16_RMI>,
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OpSize;
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def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
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(outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
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"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1), imm:$src2))],
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IIC_IMUL32_RMI>;
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def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
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(outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
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"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1),
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i32immSExt8:$src2))],
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IIC_IMUL32_RMI>;
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def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
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(outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1),
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i64immSExt32:$src2))],
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IIC_IMUL64_RMI>;
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def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
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(outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1),
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i64immSExt8:$src2))],
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IIC_IMUL64_RMI>;
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} // SchedRW
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} // Defs = [EFLAGS]
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// unsigned division/remainder
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let hasSideEffects = 1 in { // so that we don't speculatively execute
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let SchedRW = [WriteIDiv] in {
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let Defs = [AL,AH,EFLAGS], Uses = [AX] in
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def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
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"div{b}\t$src", [], IIC_DIV8_REG>;
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let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
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def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
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"div{w}\t$src", [], IIC_DIV16>, OpSize;
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
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def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
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"div{l}\t$src", [], IIC_DIV32>;
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// RDX:RAX/r64 = RAX,RDX
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
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def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
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"div{q}\t$src", [], IIC_DIV64>;
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} // SchedRW
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let mayLoad = 1 in {
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let Defs = [AL,AH,EFLAGS], Uses = [AX] in
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def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
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"div{b}\t$src", [], IIC_DIV8_MEM>,
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SchedLoadReg<WriteIDivLd>;
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let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
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def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
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"div{w}\t$src", [], IIC_DIV16>, OpSize,
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SchedLoadReg<WriteIDivLd>;
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
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def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
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"div{l}\t$src", [], IIC_DIV32>,
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SchedLoadReg<WriteIDivLd>;
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// RDX:RAX/[mem64] = RAX,RDX
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
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def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
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"div{q}\t$src", [], IIC_DIV64>,
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SchedLoadReg<WriteIDivLd>;
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}
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// Signed division/remainder.
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let SchedRW = [WriteIDiv] in {
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let Defs = [AL,AH,EFLAGS], Uses = [AX] in
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def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
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"idiv{b}\t$src", [], IIC_IDIV8>;
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let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
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|
def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
|
|
"idiv{w}\t$src", [], IIC_IDIV16>, OpSize;
|
|
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
|
|
def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
|
|
"idiv{l}\t$src", [], IIC_IDIV32>;
|
|
// RDX:RAX/r64 = RAX,RDX
|
|
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
|
|
def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
|
|
"idiv{q}\t$src", [], IIC_IDIV64>;
|
|
} // SchedRW
|
|
|
|
let mayLoad = 1 in {
|
|
let Defs = [AL,AH,EFLAGS], Uses = [AX] in
|
|
def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
|
|
"idiv{b}\t$src", [], IIC_IDIV8>,
|
|
SchedLoadReg<WriteIDivLd>;
|
|
let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
|
|
def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
|
|
"idiv{w}\t$src", [], IIC_IDIV16>, OpSize,
|
|
SchedLoadReg<WriteIDivLd>;
|
|
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
|
|
def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
|
|
"idiv{l}\t$src", [], IIC_IDIV32>,
|
|
SchedLoadReg<WriteIDivLd>;
|
|
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
|
|
def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
|
|
"idiv{q}\t$src", [], IIC_IDIV64>,
|
|
SchedLoadReg<WriteIDivLd>;
|
|
}
|
|
} // hasSideEffects = 0
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Two address Instructions.
|
|
//
|
|
|
|
// unary instructions
|
|
let CodeSize = 2 in {
|
|
let Defs = [EFLAGS] in {
|
|
let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
|
|
def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|
"neg{b}\t$dst",
|
|
[(set GR8:$dst, (ineg GR8:$src1)),
|
|
(implicit EFLAGS)], IIC_UNARY_REG>;
|
|
def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
|
"neg{w}\t$dst",
|
|
[(set GR16:$dst, (ineg GR16:$src1)),
|
|
(implicit EFLAGS)], IIC_UNARY_REG>, OpSize;
|
|
def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
|
"neg{l}\t$dst",
|
|
[(set GR32:$dst, (ineg GR32:$src1)),
|
|
(implicit EFLAGS)], IIC_UNARY_REG>;
|
|
def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
|
|
[(set GR64:$dst, (ineg GR64:$src1)),
|
|
(implicit EFLAGS)], IIC_UNARY_REG>;
|
|
} // Constraints = "$src1 = $dst", SchedRW
|
|
|
|
// Read-modify-write negate.
|
|
let SchedRW = [WriteALULd, WriteRMW] in {
|
|
def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
|
|
"neg{b}\t$dst",
|
|
[(store (ineg (loadi8 addr:$dst)), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
|
def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
|
|
"neg{w}\t$dst",
|
|
[(store (ineg (loadi16 addr:$dst)), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize;
|
|
def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
|
|
"neg{l}\t$dst",
|
|
[(store (ineg (loadi32 addr:$dst)), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
|
def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
|
|
[(store (ineg (loadi64 addr:$dst)), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
|
} // SchedRW
|
|
} // Defs = [EFLAGS]
|
|
|
|
|
|
// Note: NOT does not set EFLAGS!
|
|
|
|
let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
|
|
// Match xor -1 to not. Favors these over a move imm + xor to save code size.
|
|
let AddedComplexity = 15 in {
|
|
def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|
"not{b}\t$dst",
|
|
[(set GR8:$dst, (not GR8:$src1))], IIC_UNARY_REG>;
|
|
def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
|
"not{w}\t$dst",
|
|
[(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize;
|
|
def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
|
"not{l}\t$dst",
|
|
[(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>;
|
|
def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
|
|
[(set GR64:$dst, (not GR64:$src1))], IIC_UNARY_REG>;
|
|
}
|
|
} // Constraints = "$src1 = $dst", SchedRW
|
|
|
|
let SchedRW = [WriteALULd, WriteRMW] in {
|
|
def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
|
|
"not{b}\t$dst",
|
|
[(store (not (loadi8 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
|
|
def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
|
|
"not{w}\t$dst",
|
|
[(store (not (loadi16 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,
|
|
OpSize;
|
|
def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
|
|
"not{l}\t$dst",
|
|
[(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
|
|
def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
|
|
[(store (not (loadi64 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
|
|
} // SchedRW
|
|
} // CodeSize
|
|
|
|
// TODO: inc/dec is slow for P4, but fast for Pentium-M.
|
|
let Defs = [EFLAGS] in {
|
|
let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
|
|
let CodeSize = 2 in
|
|
def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|
"inc{b}\t$dst",
|
|
[(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))],
|
|
IIC_UNARY_REG>;
|
|
|
|
let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
|
|
def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
|
|
"inc{w}\t$dst",
|
|
[(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))], IIC_UNARY_REG>,
|
|
OpSize, Requires<[In32BitMode]>;
|
|
def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
|
|
"inc{l}\t$dst",
|
|
[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
|
|
IIC_UNARY_REG>,
|
|
Requires<[In32BitMode]>;
|
|
def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
|
|
[(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))],
|
|
IIC_UNARY_REG>;
|
|
} // isConvertibleToThreeAddress = 1, CodeSize = 1
|
|
|
|
|
|
// In 64-bit mode, single byte INC and DEC cannot be encoded.
|
|
let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
|
|
// Can transform into LEA.
|
|
def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
|
|
"inc{w}\t$dst",
|
|
[(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))],
|
|
IIC_UNARY_REG>,
|
|
OpSize, Requires<[In64BitMode]>;
|
|
def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
|
"inc{l}\t$dst",
|
|
[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
|
|
IIC_UNARY_REG>,
|
|
Requires<[In64BitMode]>;
|
|
def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
|
|
"dec{w}\t$dst",
|
|
[(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
|
|
IIC_UNARY_REG>,
|
|
OpSize, Requires<[In64BitMode]>;
|
|
def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
|
"dec{l}\t$dst",
|
|
[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
|
|
IIC_UNARY_REG>,
|
|
Requires<[In64BitMode]>;
|
|
} // isConvertibleToThreeAddress = 1, CodeSize = 2
|
|
|
|
let isCodeGenOnly = 1, CodeSize = 2 in {
|
|
def INC32_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
|
|
"inc{w}\t$dst", [], IIC_UNARY_REG>,
|
|
OpSize, Requires<[In32BitMode]>;
|
|
def INC32_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
|
"inc{l}\t$dst", [], IIC_UNARY_REG>,
|
|
Requires<[In32BitMode]>;
|
|
def DEC32_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
|
|
"dec{w}\t$dst", [], IIC_UNARY_REG>,
|
|
OpSize, Requires<[In32BitMode]>;
|
|
def DEC32_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
|
"dec{l}\t$dst", [], IIC_UNARY_REG>,
|
|
Requires<[In32BitMode]>;
|
|
} // isCodeGenOnly = 1, CodeSize = 2
|
|
|
|
} // Constraints = "$src1 = $dst", SchedRW
|
|
|
|
let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
|
|
def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
|
|
[(store (add (loadi8 addr:$dst), 1), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
|
def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
|
|
[(store (add (loadi16 addr:$dst), 1), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
|
OpSize, Requires<[In32BitMode]>;
|
|
def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
|
|
[(store (add (loadi32 addr:$dst), 1), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
|
Requires<[In32BitMode]>;
|
|
def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
|
|
[(store (add (loadi64 addr:$dst), 1), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
|
|
|
// These are duplicates of their 32-bit counterparts. Only needed so X86 knows
|
|
// how to unfold them.
|
|
// FIXME: What is this for??
|
|
def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
|
|
[(store (add (loadi16 addr:$dst), 1), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
|
OpSize, Requires<[In64BitMode]>;
|
|
def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
|
|
[(store (add (loadi32 addr:$dst), 1), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
|
Requires<[In64BitMode]>;
|
|
def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
|
|
[(store (add (loadi16 addr:$dst), -1), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
|
OpSize, Requires<[In64BitMode]>;
|
|
def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
|
|
[(store (add (loadi32 addr:$dst), -1), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
|
Requires<[In64BitMode]>;
|
|
} // CodeSize = 2, SchedRW
|
|
|
|
let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
|
|
let CodeSize = 2 in
|
|
def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|
"dec{b}\t$dst",
|
|
[(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))],
|
|
IIC_UNARY_REG>;
|
|
let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
|
|
def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
|
|
"dec{w}\t$dst",
|
|
[(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
|
|
IIC_UNARY_REG>,
|
|
OpSize, Requires<[In32BitMode]>;
|
|
def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
|
|
"dec{l}\t$dst",
|
|
[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
|
|
IIC_UNARY_REG>,
|
|
Requires<[In32BitMode]>;
|
|
def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
|
|
[(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))],
|
|
IIC_UNARY_REG>;
|
|
} // CodeSize = 2
|
|
} // Constraints = "$src1 = $dst", SchedRW
|
|
|
|
|
|
let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
|
|
def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
|
|
[(store (add (loadi8 addr:$dst), -1), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
|
def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
|
|
[(store (add (loadi16 addr:$dst), -1), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
|
OpSize, Requires<[In32BitMode]>;
|
|
def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
|
|
[(store (add (loadi32 addr:$dst), -1), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
|
Requires<[In32BitMode]>;
|
|
def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
|
|
[(store (add (loadi64 addr:$dst), -1), addr:$dst),
|
|
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
|
} // CodeSize = 2, SchedRW
|
|
} // Defs = [EFLAGS]
|
|
|
|
/// X86TypeInfo - This is a bunch of information that describes relevant X86
|
|
/// information about value types. For example, it can tell you what the
|
|
/// register class and preferred load to use.
|
|
class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
|
|
PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
|
|
Operand immoperand, SDPatternOperator immoperator,
|
|
Operand imm8operand, SDPatternOperator imm8operator,
|
|
bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> {
|
|
/// VT - This is the value type itself.
|
|
ValueType VT = vt;
|
|
|
|
/// InstrSuffix - This is the suffix used on instructions with this type. For
|
|
/// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q".
|
|
string InstrSuffix = instrsuffix;
|
|
|
|
/// RegClass - This is the register class associated with this type. For
|
|
/// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64.
|
|
RegisterClass RegClass = regclass;
|
|
|
|
/// LoadNode - This is the load node associated with this type. For
|
|
/// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64.
|
|
PatFrag LoadNode = loadnode;
|
|
|
|
/// MemOperand - This is the memory operand associated with this type. For
|
|
/// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
|
|
X86MemOperand MemOperand = memoperand;
|
|
|
|
/// ImmEncoding - This is the encoding of an immediate of this type. For
|
|
/// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32
|
|
/// since the immediate fields of i64 instructions is a 32-bit sign extended
|
|
/// value.
|
|
ImmType ImmEncoding = immkind;
|
|
|
|
/// ImmOperand - This is the operand kind of an immediate of this type. For
|
|
/// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 ->
|
|
/// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign
|
|
/// extended value.
|
|
Operand ImmOperand = immoperand;
|
|
|
|
/// ImmOperator - This is the operator that should be used to match an
|
|
/// immediate of this kind in a pattern (e.g. imm, or i64immSExt32).
|
|
SDPatternOperator ImmOperator = immoperator;
|
|
|
|
/// Imm8Operand - This is the operand kind to use for an imm8 of this type.
|
|
/// For example, i8 -> <invalid>, i16 -> i16i8imm, i32 -> i32i8imm. This is
|
|
/// only used for instructions that have a sign-extended imm8 field form.
|
|
Operand Imm8Operand = imm8operand;
|
|
|
|
/// Imm8Operator - This is the operator that should be used to match an 8-bit
|
|
/// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8).
|
|
SDPatternOperator Imm8Operator = imm8operator;
|
|
|
|
/// HasOddOpcode - This bit is true if the instruction should have an odd (as
|
|
/// opposed to even) opcode. Operations on i8 are usually even, operations on
|
|
/// other datatypes are odd.
|
|
bit HasOddOpcode = hasOddOpcode;
|
|
|
|
/// HasOpSizePrefix - This bit is set to true if the instruction should have
|
|
/// the 0x66 operand size prefix. This is set for i16 types.
|
|
bit HasOpSizePrefix = hasOpSizePrefix;
|
|
|
|
/// HasREX_WPrefix - This bit is set to true if the instruction should have
|
|
/// the 0x40 REX prefix. This is set for i64 types.
|
|
bit HasREX_WPrefix = hasREX_WPrefix;
|
|
}
|
|
|
|
def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">;
|
|
|
|
|
|
def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem ,
|
|
Imm8 , i8imm , imm, i8imm , invalid_node,
|
|
0, 0, 0>;
|
|
def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem,
|
|
Imm16, i16imm, imm, i16i8imm, i16immSExt8,
|
|
1, 1, 0>;
|
|
def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem,
|
|
Imm32, i32imm, imm, i32i8imm, i32immSExt8,
|
|
1, 0, 0>;
|
|
def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
|
|
Imm32, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
|
|
1, 0, 1>;
|
|
|
|
/// ITy - This instruction base class takes the type info for the instruction.
|
|
/// Using this, it:
|
|
/// 1. Concatenates together the instruction mnemonic with the appropriate
|
|
/// suffix letter, a tab, and the arguments.
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/// 2. Infers whether the instruction should have a 0x66 prefix byte.
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/// 3. Infers whether the instruction should have a 0x40 REX_W prefix.
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/// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations)
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/// or 1 (for i16,i32,i64 operations).
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class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
|
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string mnemonic, string args, list<dag> pattern,
|
|
InstrItinClass itin = IIC_BIN_NONMEM>
|
|
: I<{opcode{7}, opcode{6}, opcode{5}, opcode{4},
|
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opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode },
|
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f, outs, ins,
|
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!strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern,
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itin> {
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|
|
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// Infer instruction prefixes from type info.
|
|
let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
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let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
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}
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|
|
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// BinOpRR - Instructions like "add reg, reg, reg".
|
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class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
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dag outlist, list<dag> pattern, InstrItinClass itin,
|
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Format f = MRMDestReg>
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|
: ITy<opcode, f, typeinfo, outlist,
|
|
(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
|
|
mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
|
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Sched<[WriteALU]>;
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|
|
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// BinOpRR_R - Instructions like "add reg, reg, reg", where the pattern has
|
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// just a regclass (no eflags) as a result.
|
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class BinOpRR_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
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SDNode opnode>
|
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: BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
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|
[(set typeinfo.RegClass:$dst,
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(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
|
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IIC_BIN_NONMEM>;
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|
|
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// BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has
|
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// just a EFLAGS as a result.
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class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
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SDPatternOperator opnode, Format f = MRMDestReg>
|
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: BinOpRR<opcode, mnemonic, typeinfo, (outs),
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[(set EFLAGS,
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(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
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IIC_BIN_NONMEM, f>;
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|
|
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// BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has
|
|
// both a regclass and EFLAGS as a result.
|
|
class BinOpRR_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode>
|
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: BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
|
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[(set typeinfo.RegClass:$dst, EFLAGS,
|
|
(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
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IIC_BIN_NONMEM>;
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|
|
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// BinOpRR_RFF - Instructions like "adc reg, reg, reg", where the pattern has
|
|
// both a regclass and EFLAGS as a result, and has EFLAGS as input.
|
|
class BinOpRR_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode>
|
|
: BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
|
|
[(set typeinfo.RegClass:$dst, EFLAGS,
|
|
(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
|
|
EFLAGS))], IIC_BIN_CARRY_NONMEM>;
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|
|
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// BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding).
|
|
class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
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InstrItinClass itin = IIC_BIN_NONMEM>
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|
: ITy<opcode, MRMSrcReg, typeinfo,
|
|
(outs typeinfo.RegClass:$dst),
|
|
(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
|
|
mnemonic, "{$src2, $dst|$dst, $src2}", [], itin>,
|
|
Sched<[WriteALU]> {
|
|
// The disassembler should know about this, but not the asmparser.
|
|
let isCodeGenOnly = 1;
|
|
let hasSideEffects = 0;
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|
}
|
|
|
|
// BinOpRR_RDD_Rev - Instructions like "adc reg, reg, reg" (reversed encoding).
|
|
class BinOpRR_RFF_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
|
|
: BinOpRR_Rev<opcode, mnemonic, typeinfo, IIC_BIN_CARRY_NONMEM>;
|
|
|
|
// BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding).
|
|
class BinOpRR_F_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
|
|
: ITy<opcode, MRMSrcReg, typeinfo, (outs),
|
|
(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
|
|
mnemonic, "{$src2, $src1|$src1, $src2}", [], IIC_BIN_NONMEM>,
|
|
Sched<[WriteALU]> {
|
|
// The disassembler should know about this, but not the asmparser.
|
|
let isCodeGenOnly = 1;
|
|
let hasSideEffects = 0;
|
|
}
|
|
|
|
// BinOpRM - Instructions like "add reg, reg, [mem]".
|
|
class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
dag outlist, list<dag> pattern,
|
|
InstrItinClass itin = IIC_BIN_MEM>
|
|
: ITy<opcode, MRMSrcMem, typeinfo, outlist,
|
|
(ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
|
|
mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
|
|
Sched<[WriteALULd, ReadAfterLd]>;
|
|
|
|
// BinOpRM_R - Instructions like "add reg, reg, [mem]".
|
|
class BinOpRM_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode>
|
|
: BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
|
|
[(set typeinfo.RegClass:$dst,
|
|
(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
|
|
|
|
// BinOpRM_F - Instructions like "cmp reg, [mem]".
|
|
class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDPatternOperator opnode>
|
|
: BinOpRM<opcode, mnemonic, typeinfo, (outs),
|
|
[(set EFLAGS,
|
|
(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
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|
|
|
// BinOpRM_RF - Instructions like "add reg, reg, [mem]".
|
|
class BinOpRM_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode>
|
|
: BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
|
|
[(set typeinfo.RegClass:$dst, EFLAGS,
|
|
(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
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|
|
|
// BinOpRM_RFF - Instructions like "adc reg, reg, [mem]".
|
|
class BinOpRM_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode>
|
|
: BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
|
|
[(set typeinfo.RegClass:$dst, EFLAGS,
|
|
(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2),
|
|
EFLAGS))], IIC_BIN_CARRY_MEM>;
|
|
|
|
// BinOpRI - Instructions like "add reg, reg, imm".
|
|
class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
Format f, dag outlist, list<dag> pattern,
|
|
InstrItinClass itin = IIC_BIN_NONMEM>
|
|
: ITy<opcode, f, typeinfo, outlist,
|
|
(ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
|
|
mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
|
|
Sched<[WriteALU]> {
|
|
let ImmT = typeinfo.ImmEncoding;
|
|
}
|
|
|
|
// BinOpRI_R - Instructions like "add reg, reg, imm".
|
|
class BinOpRI_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode, Format f>
|
|
: BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
|
|
[(set typeinfo.RegClass:$dst,
|
|
(opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
|
|
|
|
// BinOpRI_F - Instructions like "cmp reg, imm".
|
|
class BinOpRI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDPatternOperator opnode, Format f>
|
|
: BinOpRI<opcode, mnemonic, typeinfo, f, (outs),
|
|
[(set EFLAGS,
|
|
(opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
|
|
|
|
// BinOpRI_RF - Instructions like "add reg, reg, imm".
|
|
class BinOpRI_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode, Format f>
|
|
: BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
|
|
[(set typeinfo.RegClass:$dst, EFLAGS,
|
|
(opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
|
|
// BinOpRI_RFF - Instructions like "adc reg, reg, imm".
|
|
class BinOpRI_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode, Format f>
|
|
: BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
|
|
[(set typeinfo.RegClass:$dst, EFLAGS,
|
|
(opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2,
|
|
EFLAGS))], IIC_BIN_CARRY_NONMEM>;
|
|
|
|
// BinOpRI8 - Instructions like "add reg, reg, imm8".
|
|
class BinOpRI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
Format f, dag outlist, list<dag> pattern,
|
|
InstrItinClass itin = IIC_BIN_NONMEM>
|
|
: ITy<opcode, f, typeinfo, outlist,
|
|
(ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2),
|
|
mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
|
|
Sched<[WriteALU]> {
|
|
let ImmT = Imm8; // Always 8-bit immediate.
|
|
}
|
|
|
|
// BinOpRI8_R - Instructions like "add reg, reg, imm8".
|
|
class BinOpRI8_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode, Format f>
|
|
: BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
|
|
[(set typeinfo.RegClass:$dst,
|
|
(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
|
|
|
|
// BinOpRI8_F - Instructions like "cmp reg, imm8".
|
|
class BinOpRI8_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode, Format f>
|
|
: BinOpRI8<opcode, mnemonic, typeinfo, f, (outs),
|
|
[(set EFLAGS,
|
|
(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
|
|
|
|
// BinOpRI8_RF - Instructions like "add reg, reg, imm8".
|
|
class BinOpRI8_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode, Format f>
|
|
: BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
|
|
[(set typeinfo.RegClass:$dst, EFLAGS,
|
|
(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
|
|
|
|
// BinOpRI8_RFF - Instructions like "adc reg, reg, imm8".
|
|
class BinOpRI8_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode, Format f>
|
|
: BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
|
|
[(set typeinfo.RegClass:$dst, EFLAGS,
|
|
(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2,
|
|
EFLAGS))], IIC_BIN_CARRY_NONMEM>;
|
|
|
|
// BinOpMR - Instructions like "add [mem], reg".
|
|
class BinOpMR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
list<dag> pattern, InstrItinClass itin = IIC_BIN_MEM>
|
|
: ITy<opcode, MRMDestMem, typeinfo,
|
|
(outs), (ins typeinfo.MemOperand:$dst, typeinfo.RegClass:$src),
|
|
mnemonic, "{$src, $dst|$dst, $src}", pattern, itin>,
|
|
Sched<[WriteALULd, WriteRMW]>;
|
|
|
|
// BinOpMR_RMW - Instructions like "add [mem], reg".
|
|
class BinOpMR_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode>
|
|
: BinOpMR<opcode, mnemonic, typeinfo,
|
|
[(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
|
|
// BinOpMR_RMW_FF - Instructions like "adc [mem], reg".
|
|
class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode>
|
|
: BinOpMR<opcode, mnemonic, typeinfo,
|
|
[(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS),
|
|
addr:$dst),
|
|
(implicit EFLAGS)], IIC_BIN_CARRY_MEM>;
|
|
|
|
// BinOpMR_F - Instructions like "cmp [mem], reg".
|
|
class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode>
|
|
: BinOpMR<opcode, mnemonic, typeinfo,
|
|
[(set EFLAGS, (opnode (load addr:$dst), typeinfo.RegClass:$src))]>;
|
|
|
|
// BinOpMI - Instructions like "add [mem], imm".
|
|
class BinOpMI<string mnemonic, X86TypeInfo typeinfo,
|
|
Format f, list<dag> pattern, bits<8> opcode = 0x80,
|
|
InstrItinClass itin = IIC_BIN_MEM>
|
|
: ITy<opcode, f, typeinfo,
|
|
(outs), (ins typeinfo.MemOperand:$dst, typeinfo.ImmOperand:$src),
|
|
mnemonic, "{$src, $dst|$dst, $src}", pattern, itin>,
|
|
Sched<[WriteALULd, WriteRMW]> {
|
|
let ImmT = typeinfo.ImmEncoding;
|
|
}
|
|
|
|
// BinOpMI_RMW - Instructions like "add [mem], imm".
|
|
class BinOpMI_RMW<string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode, Format f>
|
|
: BinOpMI<mnemonic, typeinfo, f,
|
|
[(store (opnode (typeinfo.VT (load addr:$dst)),
|
|
typeinfo.ImmOperator:$src), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
// BinOpMI_RMW_FF - Instructions like "adc [mem], imm".
|
|
class BinOpMI_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode, Format f>
|
|
: BinOpMI<mnemonic, typeinfo, f,
|
|
[(store (opnode (typeinfo.VT (load addr:$dst)),
|
|
typeinfo.ImmOperator:$src, EFLAGS), addr:$dst),
|
|
(implicit EFLAGS)], 0x80, IIC_BIN_CARRY_MEM>;
|
|
|
|
// BinOpMI_F - Instructions like "cmp [mem], imm".
|
|
class BinOpMI_F<string mnemonic, X86TypeInfo typeinfo,
|
|
SDPatternOperator opnode, Format f, bits<8> opcode = 0x80>
|
|
: BinOpMI<mnemonic, typeinfo, f,
|
|
[(set EFLAGS, (opnode (typeinfo.VT (load addr:$dst)),
|
|
typeinfo.ImmOperator:$src))],
|
|
opcode>;
|
|
|
|
// BinOpMI8 - Instructions like "add [mem], imm8".
|
|
class BinOpMI8<string mnemonic, X86TypeInfo typeinfo,
|
|
Format f, list<dag> pattern,
|
|
InstrItinClass itin = IIC_BIN_MEM>
|
|
: ITy<0x82, f, typeinfo,
|
|
(outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src),
|
|
mnemonic, "{$src, $dst|$dst, $src}", pattern, itin>,
|
|
Sched<[WriteALULd, WriteRMW]> {
|
|
let ImmT = Imm8; // Always 8-bit immediate.
|
|
}
|
|
|
|
// BinOpMI8_RMW - Instructions like "add [mem], imm8".
|
|
class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode, Format f>
|
|
: BinOpMI8<mnemonic, typeinfo, f,
|
|
[(store (opnode (load addr:$dst),
|
|
typeinfo.Imm8Operator:$src), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
|
|
// BinOpMI8_RMW_FF - Instructions like "adc [mem], imm8".
|
|
class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode, Format f>
|
|
: BinOpMI8<mnemonic, typeinfo, f,
|
|
[(store (opnode (load addr:$dst),
|
|
typeinfo.Imm8Operator:$src, EFLAGS), addr:$dst),
|
|
(implicit EFLAGS)], IIC_BIN_CARRY_MEM>;
|
|
|
|
// BinOpMI8_F - Instructions like "cmp [mem], imm8".
|
|
class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
|
|
SDNode opnode, Format f>
|
|
: BinOpMI8<mnemonic, typeinfo, f,
|
|
[(set EFLAGS, (opnode (load addr:$dst),
|
|
typeinfo.Imm8Operator:$src))]>;
|
|
|
|
// BinOpAI - Instructions like "add %eax, %eax, imm", that imp-def EFLAGS.
|
|
class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
Register areg, string operands,
|
|
InstrItinClass itin = IIC_BIN_NONMEM>
|
|
: ITy<opcode, RawFrm, typeinfo,
|
|
(outs), (ins typeinfo.ImmOperand:$src),
|
|
mnemonic, operands, [], itin>, Sched<[WriteALU]> {
|
|
let ImmT = typeinfo.ImmEncoding;
|
|
let Uses = [areg];
|
|
let Defs = [areg, EFLAGS];
|
|
let hasSideEffects = 0;
|
|
}
|
|
|
|
// BinOpAI_FF - Instructions like "adc %eax, %eax, imm", that implicitly define
|
|
// and use EFLAGS.
|
|
class BinOpAI_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
|
|
Register areg, string operands>
|
|
: BinOpAI<opcode, mnemonic, typeinfo, areg, operands,
|
|
IIC_BIN_CARRY_NONMEM> {
|
|
let Uses = [areg, EFLAGS];
|
|
}
|
|
|
|
/// ArithBinOp_RF - This is an arithmetic binary operator where the pattern is
|
|
/// defined with "(set GPR:$dst, EFLAGS, (...".
|
|
///
|
|
/// It would be nice to get rid of the second and third argument here, but
|
|
/// tblgen can't handle dependent type references aggressively enough: PR8330
|
|
multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
|
|
string mnemonic, Format RegMRM, Format MemMRM,
|
|
SDNode opnodeflag, SDNode opnode,
|
|
bit CommutableRR, bit ConvertibleToThreeAddress> {
|
|
let Defs = [EFLAGS] in {
|
|
let Constraints = "$src1 = $dst" in {
|
|
let isCommutable = CommutableRR,
|
|
isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
|
|
def NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
|
|
def NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>;
|
|
def NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>;
|
|
def NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
|
|
} // isCommutable
|
|
|
|
def NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
|
|
def NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
|
|
def NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
|
|
def NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
|
|
|
|
def NAME#8rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi8 , opnodeflag>;
|
|
def NAME#16rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi16, opnodeflag>;
|
|
def NAME#32rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi32, opnodeflag>;
|
|
def NAME#64rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi64, opnodeflag>;
|
|
|
|
let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
|
|
// NOTE: These are order specific, we want the ri8 forms to be listed
|
|
// first so that they are slightly preferred to the ri forms.
|
|
def NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>;
|
|
def NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>;
|
|
def NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>;
|
|
|
|
def NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
|
|
def NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>;
|
|
def NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>;
|
|
def NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>;
|
|
}
|
|
} // Constraints = "$src1 = $dst"
|
|
|
|
def NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
|
|
def NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
|
|
def NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
|
|
def NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
|
|
|
|
// NOTE: These are order specific, we want the mi8 forms to be listed
|
|
// first so that they are slightly preferred to the mi forms.
|
|
def NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>;
|
|
def NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>;
|
|
def NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>;
|
|
|
|
def NAME#8mi : BinOpMI_RMW<mnemonic, Xi8 , opnode, MemMRM>;
|
|
def NAME#16mi : BinOpMI_RMW<mnemonic, Xi16, opnode, MemMRM>;
|
|
def NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>;
|
|
def NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>;
|
|
} // Defs = [EFLAGS]
|
|
|
|
def NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
|
|
"{$src, %al|al, $src}">;
|
|
def NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
|
|
"{$src, %ax|ax, $src}">;
|
|
def NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
|
|
"{$src, %eax|eax, $src}">;
|
|
def NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
|
|
"{$src, %rax|rax, $src}">;
|
|
}
|
|
|
|
/// ArithBinOp_RFF - This is an arithmetic binary operator where the pattern is
|
|
/// defined with "(set GPR:$dst, EFLAGS, (node LHS, RHS, EFLAGS))" like ADC and
|
|
/// SBB.
|
|
///
|
|
/// It would be nice to get rid of the second and third argument here, but
|
|
/// tblgen can't handle dependent type references aggressively enough: PR8330
|
|
multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
|
|
string mnemonic, Format RegMRM, Format MemMRM,
|
|
SDNode opnode, bit CommutableRR,
|
|
bit ConvertibleToThreeAddress> {
|
|
let Uses = [EFLAGS], Defs = [EFLAGS] in {
|
|
let Constraints = "$src1 = $dst" in {
|
|
let isCommutable = CommutableRR,
|
|
isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
|
|
def NAME#8rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi8 , opnode>;
|
|
def NAME#16rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi16, opnode>;
|
|
def NAME#32rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi32, opnode>;
|
|
def NAME#64rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi64, opnode>;
|
|
} // isCommutable
|
|
|
|
def NAME#8rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi8>;
|
|
def NAME#16rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi16>;
|
|
def NAME#32rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi32>;
|
|
def NAME#64rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi64>;
|
|
|
|
def NAME#8rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi8 , opnode>;
|
|
def NAME#16rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi16, opnode>;
|
|
def NAME#32rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi32, opnode>;
|
|
def NAME#64rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi64, opnode>;
|
|
|
|
let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
|
|
// NOTE: These are order specific, we want the ri8 forms to be listed
|
|
// first so that they are slightly preferred to the ri forms.
|
|
def NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, opnode, RegMRM>;
|
|
def NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, opnode, RegMRM>;
|
|
def NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, opnode, RegMRM>;
|
|
|
|
def NAME#8ri : BinOpRI_RFF<0x80, mnemonic, Xi8 , opnode, RegMRM>;
|
|
def NAME#16ri : BinOpRI_RFF<0x80, mnemonic, Xi16, opnode, RegMRM>;
|
|
def NAME#32ri : BinOpRI_RFF<0x80, mnemonic, Xi32, opnode, RegMRM>;
|
|
def NAME#64ri32: BinOpRI_RFF<0x80, mnemonic, Xi64, opnode, RegMRM>;
|
|
}
|
|
} // Constraints = "$src1 = $dst"
|
|
|
|
def NAME#8mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi8 , opnode>;
|
|
def NAME#16mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi16, opnode>;
|
|
def NAME#32mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi32, opnode>;
|
|
def NAME#64mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi64, opnode>;
|
|
|
|
// NOTE: These are order specific, we want the mi8 forms to be listed
|
|
// first so that they are slightly preferred to the mi forms.
|
|
def NAME#16mi8 : BinOpMI8_RMW_FF<mnemonic, Xi16, opnode, MemMRM>;
|
|
def NAME#32mi8 : BinOpMI8_RMW_FF<mnemonic, Xi32, opnode, MemMRM>;
|
|
def NAME#64mi8 : BinOpMI8_RMW_FF<mnemonic, Xi64, opnode, MemMRM>;
|
|
|
|
def NAME#8mi : BinOpMI_RMW_FF<mnemonic, Xi8 , opnode, MemMRM>;
|
|
def NAME#16mi : BinOpMI_RMW_FF<mnemonic, Xi16, opnode, MemMRM>;
|
|
def NAME#32mi : BinOpMI_RMW_FF<mnemonic, Xi32, opnode, MemMRM>;
|
|
def NAME#64mi32 : BinOpMI_RMW_FF<mnemonic, Xi64, opnode, MemMRM>;
|
|
} // Uses = [EFLAGS], Defs = [EFLAGS]
|
|
|
|
def NAME#8i8 : BinOpAI_FF<BaseOpc4, mnemonic, Xi8 , AL,
|
|
"{$src, %al|al, $src}">;
|
|
def NAME#16i16 : BinOpAI_FF<BaseOpc4, mnemonic, Xi16, AX,
|
|
"{$src, %ax|ax, $src}">;
|
|
def NAME#32i32 : BinOpAI_FF<BaseOpc4, mnemonic, Xi32, EAX,
|
|
"{$src, %eax|eax, $src}">;
|
|
def NAME#64i32 : BinOpAI_FF<BaseOpc4, mnemonic, Xi64, RAX,
|
|
"{$src, %rax|rax, $src}">;
|
|
}
|
|
|
|
/// ArithBinOp_F - This is an arithmetic binary operator where the pattern is
|
|
/// defined with "(set EFLAGS, (...". It would be really nice to find a way
|
|
/// to factor this with the other ArithBinOp_*.
|
|
///
|
|
multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
|
|
string mnemonic, Format RegMRM, Format MemMRM,
|
|
SDNode opnode,
|
|
bit CommutableRR, bit ConvertibleToThreeAddress> {
|
|
let Defs = [EFLAGS] in {
|
|
let isCommutable = CommutableRR,
|
|
isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
|
|
def NAME#8rr : BinOpRR_F<BaseOpc, mnemonic, Xi8 , opnode>;
|
|
def NAME#16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>;
|
|
def NAME#32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>;
|
|
def NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
|
|
} // isCommutable
|
|
|
|
def NAME#8rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi8>;
|
|
def NAME#16rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi16>;
|
|
def NAME#32rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi32>;
|
|
def NAME#64rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi64>;
|
|
|
|
def NAME#8rm : BinOpRM_F<BaseOpc2, mnemonic, Xi8 , opnode>;
|
|
def NAME#16rm : BinOpRM_F<BaseOpc2, mnemonic, Xi16, opnode>;
|
|
def NAME#32rm : BinOpRM_F<BaseOpc2, mnemonic, Xi32, opnode>;
|
|
def NAME#64rm : BinOpRM_F<BaseOpc2, mnemonic, Xi64, opnode>;
|
|
|
|
let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
|
|
// NOTE: These are order specific, we want the ri8 forms to be listed
|
|
// first so that they are slightly preferred to the ri forms.
|
|
def NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>;
|
|
def NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>;
|
|
def NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>;
|
|
|
|
def NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>;
|
|
def NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>;
|
|
def NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>;
|
|
def NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>;
|
|
}
|
|
|
|
def NAME#8mr : BinOpMR_F<BaseOpc, mnemonic, Xi8 , opnode>;
|
|
def NAME#16mr : BinOpMR_F<BaseOpc, mnemonic, Xi16, opnode>;
|
|
def NAME#32mr : BinOpMR_F<BaseOpc, mnemonic, Xi32, opnode>;
|
|
def NAME#64mr : BinOpMR_F<BaseOpc, mnemonic, Xi64, opnode>;
|
|
|
|
// NOTE: These are order specific, we want the mi8 forms to be listed
|
|
// first so that they are slightly preferred to the mi forms.
|
|
def NAME#16mi8 : BinOpMI8_F<mnemonic, Xi16, opnode, MemMRM>;
|
|
def NAME#32mi8 : BinOpMI8_F<mnemonic, Xi32, opnode, MemMRM>;
|
|
def NAME#64mi8 : BinOpMI8_F<mnemonic, Xi64, opnode, MemMRM>;
|
|
|
|
def NAME#8mi : BinOpMI_F<mnemonic, Xi8 , opnode, MemMRM>;
|
|
def NAME#16mi : BinOpMI_F<mnemonic, Xi16, opnode, MemMRM>;
|
|
def NAME#32mi : BinOpMI_F<mnemonic, Xi32, opnode, MemMRM>;
|
|
def NAME#64mi32 : BinOpMI_F<mnemonic, Xi64, opnode, MemMRM>;
|
|
} // Defs = [EFLAGS]
|
|
|
|
def NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
|
|
"{$src, %al|al, $src}">;
|
|
def NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
|
|
"{$src, %ax|ax, $src}">;
|
|
def NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
|
|
"{$src, %eax|eax, $src}">;
|
|
def NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
|
|
"{$src, %rax|rax, $src}">;
|
|
}
|
|
|
|
|
|
defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
|
|
X86and_flag, and, 1, 0>;
|
|
defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
|
|
X86or_flag, or, 1, 0>;
|
|
defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m,
|
|
X86xor_flag, xor, 1, 0>;
|
|
defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
|
|
X86add_flag, add, 1, 1>;
|
|
let isCompare = 1 in {
|
|
defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
|
|
X86sub_flag, sub, 0, 0>;
|
|
}
|
|
|
|
// Arithmetic.
|
|
defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag,
|
|
1, 0>;
|
|
defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag,
|
|
0, 0>;
|
|
|
|
let isCompare = 1 in {
|
|
defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Semantically, test instructions are similar like AND, except they don't
|
|
// generate a result. From an encoding perspective, they are very different:
|
|
// they don't have all the usual imm8 and REV forms, and are encoded into a
|
|
// different space.
|
|
def X86testpat : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(X86cmp (and_su node:$lhs, node:$rhs), 0)>;
|
|
|
|
let isCompare = 1 in {
|
|
let Defs = [EFLAGS] in {
|
|
let isCommutable = 1 in {
|
|
def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat, MRMSrcReg>;
|
|
def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>;
|
|
def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>;
|
|
def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat, MRMSrcReg>;
|
|
} // isCommutable
|
|
|
|
def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;
|
|
def TEST16rm : BinOpRM_F<0x84, "test", Xi16, X86testpat>;
|
|
def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>;
|
|
def TEST64rm : BinOpRM_F<0x84, "test", Xi64, X86testpat>;
|
|
|
|
def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
|
|
def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
|
|
def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
|
|
def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
|
|
|
|
def TEST8mi : BinOpMI_F<"test", Xi8 , X86testpat, MRM0m, 0xF6>;
|
|
def TEST16mi : BinOpMI_F<"test", Xi16, X86testpat, MRM0m, 0xF6>;
|
|
def TEST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>;
|
|
def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>;
|
|
|
|
// When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the
|
|
// register class is constrained to GR8_NOREX.
|
|
let isPseudo = 1 in
|
|
def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask),
|
|
"", [], IIC_BIN_NONMEM>, Sched<[WriteALU]>;
|
|
} // Defs = [EFLAGS]
|
|
|
|
def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL,
|
|
"{$src, %al|al, $src}">;
|
|
def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX,
|
|
"{$src, %ax|ax, $src}">;
|
|
def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX,
|
|
"{$src, %eax|eax, $src}">;
|
|
def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX,
|
|
"{$src, %rax|rax, $src}">;
|
|
} // isCompare
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ANDN Instruction
|
|
//
|
|
multiclass bmi_andn<string mnemonic, RegisterClass RC, X86MemOperand x86memop,
|
|
PatFrag ld_frag> {
|
|
def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
|
|
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))],
|
|
IIC_BIN_NONMEM>, Sched<[WriteALU]>;
|
|
def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
|
|
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(set RC:$dst, EFLAGS,
|
|
(X86and_flag (not RC:$src1), (ld_frag addr:$src2)))], IIC_BIN_MEM>,
|
|
Sched<[WriteALULd, ReadAfterLd]>;
|
|
}
|
|
|
|
let Predicates = [HasBMI], Defs = [EFLAGS] in {
|
|
defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8, VEX_4V;
|
|
defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8, VEX_4V, VEX_W;
|
|
}
|
|
|
|
let Predicates = [HasBMI] in {
|
|
def : Pat<(and (not GR32:$src1), GR32:$src2),
|
|
(ANDN32rr GR32:$src1, GR32:$src2)>;
|
|
def : Pat<(and (not GR64:$src1), GR64:$src2),
|
|
(ANDN64rr GR64:$src1, GR64:$src2)>;
|
|
def : Pat<(and (not GR32:$src1), (loadi32 addr:$src2)),
|
|
(ANDN32rm GR32:$src1, addr:$src2)>;
|
|
def : Pat<(and (not GR64:$src1), (loadi64 addr:$src2)),
|
|
(ANDN64rm GR64:$src1, addr:$src2)>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MULX Instruction
|
|
//
|
|
multiclass bmi_mulx<string mnemonic, RegisterClass RC, X86MemOperand x86memop> {
|
|
let neverHasSideEffects = 1 in {
|
|
let isCommutable = 1 in
|
|
def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
|
|
!strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
|
|
[], IIC_MUL8>, T8XD, VEX_4V, Sched<[WriteIMul, WriteIMulH]>;
|
|
|
|
let mayLoad = 1 in
|
|
def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src),
|
|
!strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
|
|
[], IIC_MUL8>, T8XD, VEX_4V, Sched<[WriteIMulLd, WriteIMulH]>;
|
|
}
|
|
}
|
|
|
|
let Predicates = [HasBMI2] in {
|
|
let Uses = [EDX] in
|
|
defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem>;
|
|
let Uses = [RDX] in
|
|
defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem>, VEX_W;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ADCX Instruction
|
|
//
|
|
let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
|
|
let SchedRW = [WriteALU] in {
|
|
def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|
"adcx{l}\t{$src, $dst|$dst, $src}",
|
|
[], IIC_BIN_NONMEM>, T8, OpSize;
|
|
|
|
def ADCX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
|
"adcx{q}\t{$src, $dst|$dst, $src}",
|
|
[], IIC_BIN_NONMEM>, T8, OpSize, REX_W, Requires<[In64BitMode]>;
|
|
} // SchedRW
|
|
|
|
let mayLoad = 1, SchedRW = [WriteALULd] in {
|
|
def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|
"adcx{l}\t{$src, $dst|$dst, $src}",
|
|
[], IIC_BIN_MEM>, T8, OpSize;
|
|
|
|
def ADCX64rm : I<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
|
"adcx{q}\t{$src, $dst|$dst, $src}",
|
|
[], IIC_BIN_MEM>, T8, OpSize, REX_W, Requires<[In64BitMode]>;
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ADOX Instruction
|
|
//
|
|
let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
|
|
let SchedRW = [WriteALU] in {
|
|
def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|
"adox{l}\t{$src, $dst|$dst, $src}",
|
|
[], IIC_BIN_NONMEM>, T8XS;
|
|
|
|
def ADOX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
|
"adox{q}\t{$src, $dst|$dst, $src}",
|
|
[], IIC_BIN_NONMEM>, T8XS, REX_W, Requires<[In64BitMode]>;
|
|
} // SchedRW
|
|
|
|
let mayLoad = 1, SchedRW = [WriteALULd] in {
|
|
def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|
"adox{l}\t{$src, $dst|$dst, $src}",
|
|
[], IIC_BIN_MEM>, T8XS;
|
|
|
|
def ADOX64rm : I<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
|
"adox{q}\t{$src, $dst|$dst, $src}",
|
|
[], IIC_BIN_MEM>, T8XS, REX_W, Requires<[In64BitMode]>;
|
|
}
|
|
}
|