mirror of
https://github.com/c64scene-ar/llvm-6502.git
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db8d56b825
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52923 91177308-0d34-0410-b5e6-96231b3b80d8
410 lines
12 KiB
C++
410 lines
12 KiB
C++
//===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MIPS target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-isel"
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#include "Mips.h"
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#include "MipsISelLowering.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include <queue>
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#include <set>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
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// instructions for SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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namespace {
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class VISIBILITY_HIDDEN MipsDAGToDAGISel : public SelectionDAGISel {
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/// TM - Keep a reference to MipsTargetMachine.
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MipsTargetMachine &TM;
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/// MipsLowering - This object fully describes how to lower LLVM code to an
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/// Mips-specific SelectionDAG.
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MipsTargetLowering MipsLowering;
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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//TODO: add initialization on constructor
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//const MipsSubtarget *Subtarget;
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public:
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MipsDAGToDAGISel(MipsTargetMachine &tm) :
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SelectionDAGISel(MipsLowering),
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TM(tm), MipsLowering(*TM.getTargetLowering()) {}
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virtual void InstructionSelect(SelectionDAG &SD);
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// Pass Name
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virtual const char *getPassName() const {
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return "MIPS DAG->DAG Pattern Instruction Selection";
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}
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private:
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// Include the pieces autogenerated from the target description.
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#include "MipsGenDAGISel.inc"
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SDOperand getGlobalBaseReg();
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SDNode *Select(SDOperand N);
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// Complex Pattern.
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bool SelectAddr(SDOperand Op, SDOperand N,
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SDOperand &Base, SDOperand &Offset);
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// getI32Imm - Return a target constant with the specified
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// value, of type i32.
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inline SDOperand getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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#ifndef NDEBUG
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unsigned Indent;
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#endif
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};
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}
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void MipsDAGToDAGISel::
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InstructionSelect(SelectionDAG &SD)
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{
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DEBUG(BB->dump());
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// Codegen the basic block.
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#ifndef NDEBUG
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DOUT << "===== Instruction selection begins:\n";
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Indent = 0;
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#endif
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// Select target instructions for the DAG.
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SD.setRoot(SelectRoot(SD.getRoot()));
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#ifndef NDEBUG
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DOUT << "===== Instruction selection ends:\n";
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#endif
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SD.RemoveDeadNodes();
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// GOT address into a register.
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SDOperand MipsDAGToDAGISel::getGlobalBaseReg() {
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MachineFunction* MF = BB->getParent();
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unsigned GP = 0;
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for(MachineRegisterInfo::livein_iterator ii = MF->getRegInfo().livein_begin(),
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ee = MF->getRegInfo().livein_end(); ii != ee; ++ii)
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if (ii->first == Mips::GP) {
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GP = ii->second;
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break;
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}
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assert(GP && "GOT PTR not in liveins");
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return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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GP, MVT::i32);
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}
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/// ComplexPattern used on MipsInstrInfo
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/// Used on Mips Load/Store instructions
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bool MipsDAGToDAGISel::
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SelectAddr(SDOperand Op, SDOperand Addr, SDOperand &Offset, SDOperand &Base)
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{
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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// on PIC code Load GA
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if (TM.getRelocationModel() == Reloc::PIC_) {
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if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
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(Addr.getOpcode() == ISD::TargetJumpTable)){
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Base = CurDAG->getRegister(Mips::GP, MVT::i32);
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Offset = Addr;
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return true;
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}
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} else {
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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}
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// Operand is a result from an ADD.
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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if (Predicate_immSExt16(CN)) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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} else {
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Base = Addr.getOperand(0);
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}
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Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
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return true;
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}
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}
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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/// Select instructions not customized! Used for
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/// expanded, promoted and normal instructions
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SDNode* MipsDAGToDAGISel::
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Select(SDOperand N)
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{
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SDNode *Node = N.Val;
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unsigned Opcode = Node->getOpcode();
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// Dump information about the Node being selected
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#ifndef NDEBUG
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DOUT << std::string(Indent, ' ') << "Selecting: ";
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DEBUG(Node->dump(CurDAG));
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DOUT << "\n";
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Indent += 2;
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#endif
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// If we have a custom node, we already have selected!
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if (Opcode >= ISD::BUILTIN_OP_END && Opcode < MipsISD::FIRST_NUMBER) {
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "== ";
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DEBUG(Node->dump(CurDAG));
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DOUT << "\n";
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Indent -= 2;
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#endif
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return NULL;
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}
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///
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// Instruction Selection not handled by the auto-generated
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// tablegen selection should be handled here.
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///
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switch(Opcode) {
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default: break;
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case ISD::SUBE:
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case ISD::ADDE: {
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SDOperand InFlag = Node->getOperand(2), CmpLHS;
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unsigned Opc = InFlag.getOpcode(), MOp;
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assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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(Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
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"(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
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if (Opcode == ISD::ADDE) {
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CmpLHS = InFlag.getValue(0);
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MOp = Mips::ADDu;
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} else {
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CmpLHS = InFlag.getOperand(0);
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MOp = Mips::SUBu;
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}
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SDOperand Ops[] = { CmpLHS, InFlag.getOperand(1) };
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SDOperand LHS = Node->getOperand(0);
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SDOperand RHS = Node->getOperand(1);
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AddToISelQueue(LHS);
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AddToISelQueue(RHS);
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MVT VT = LHS.getValueType();
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SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2);
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SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT,
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SDOperand(Carry,0), RHS);
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return CurDAG->SelectNodeTo(N.Val, MOp, VT, MVT::Flag,
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LHS, SDOperand(AddCarry,0));
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}
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/// Mul/Div with two results
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case ISD::SDIVREM:
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case ISD::UDIVREM:
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case ISD::SMUL_LOHI:
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case ISD::UMUL_LOHI: {
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SDOperand Op1 = Node->getOperand(0);
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SDOperand Op2 = Node->getOperand(1);
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AddToISelQueue(Op1);
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AddToISelQueue(Op2);
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unsigned Op;
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if (Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI)
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Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
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else
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Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
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SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
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SDOperand InFlag = SDOperand(Node, 0);
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SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, MVT::i32, MVT::Flag, InFlag);
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InFlag = SDOperand(Lo,1);
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SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag);
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if (!N.getValue(0).use_empty())
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ReplaceUses(N.getValue(0), SDOperand(Lo,0));
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if (!N.getValue(1).use_empty())
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ReplaceUses(N.getValue(1), SDOperand(Hi,0));
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return NULL;
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}
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/// Special Muls
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case ISD::MUL:
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case ISD::MULHS:
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case ISD::MULHU: {
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SDOperand MulOp1 = Node->getOperand(0);
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SDOperand MulOp2 = Node->getOperand(1);
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AddToISelQueue(MulOp1);
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AddToISelQueue(MulOp2);
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unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
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SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2);
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SDOperand InFlag = SDOperand(MulNode, 0);
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if (MulOp == ISD::MUL)
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return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, InFlag);
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else
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return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag);
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}
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/// Div/Rem operations
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case ISD::SREM:
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case ISD::UREM:
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case ISD::SDIV:
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case ISD::UDIV: {
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SDOperand Op1 = Node->getOperand(0);
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SDOperand Op2 = Node->getOperand(1);
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AddToISelQueue(Op1);
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AddToISelQueue(Op2);
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unsigned Op, MOp;
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if (Opcode == ISD::SDIV || Opcode == ISD::UDIV) {
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Op = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
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MOp = Mips::MFLO;
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} else {
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Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
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MOp = Mips::MFHI;
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}
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SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
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SDOperand InFlag = SDOperand(Node, 0);
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return CurDAG->getTargetNode(MOp, MVT::i32, InFlag);
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}
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// Get target GOT address.
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case ISD::GLOBAL_OFFSET_TABLE: {
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SDOperand Result = getGlobalBaseReg();
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ReplaceUses(N, Result);
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return NULL;
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}
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/// Handle direct and indirect calls when using PIC. On PIC, when
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/// GOT is smaller than about 64k (small code) the GA target is
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/// loaded with only one instruction. Otherwise GA's target must
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/// be loaded with 3 instructions.
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case MipsISD::JmpLink: {
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if (TM.getRelocationModel() == Reloc::PIC_) {
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//bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
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SDOperand Chain = Node->getOperand(0);
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SDOperand Callee = Node->getOperand(1);
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AddToISelQueue(Chain);
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SDOperand T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
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SDOperand InFlag(0, 0);
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if ( (isa<GlobalAddressSDNode>(Callee)) ||
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(isa<ExternalSymbolSDNode>(Callee)) )
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{
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/// Direct call for global addresses and external symbols
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SDOperand GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
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// Use load to get GOT target
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SDOperand Ops[] = { Callee, GPReg, Chain };
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SDOperand Load = SDOperand(CurDAG->getTargetNode(Mips::LW, MVT::i32,
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MVT::Other, Ops, 3), 0);
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Chain = Load.getValue(1);
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AddToISelQueue(Chain);
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// Call target must be on T9
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Chain = CurDAG->getCopyToReg(Chain, T9Reg, Load, InFlag);
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} else
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/// Indirect call
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Chain = CurDAG->getCopyToReg(Chain, T9Reg, Callee, InFlag);
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AddToISelQueue(Chain);
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// Emit Jump and Link Register
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SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, MVT::Other,
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MVT::Flag, T9Reg, Chain);
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Chain = SDOperand(ResNode, 0);
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InFlag = SDOperand(ResNode, 1);
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ReplaceUses(SDOperand(Node, 0), Chain);
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ReplaceUses(SDOperand(Node, 1), InFlag);
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return ResNode;
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}
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}
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}
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// Select the default instruction
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SDNode *ResNode = SelectCode(N);
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "=> ";
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if (ResNode == NULL || ResNode == N.Val)
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DEBUG(N.Val->dump(CurDAG));
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else
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DEBUG(ResNode->dump(CurDAG));
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DOUT << "\n";
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Indent -= 2;
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#endif
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return ResNode;
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}
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/// createMipsISelDag - This pass converts a legalized DAG into a
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/// MIPS-specific DAG, ready for instruction scheduling.
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FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
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return new MipsDAGToDAGISel(TM);
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}
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