llvm-6502/test/MC/X86/x86_errors.s
David Woodhouse ab5b9489e9 [x86] Make AsmParser validate registers for memory operands a bit better
We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit
mode, for example, because it might be used for an unofficial form of
the in/out instructions. We actually want to do a better job of validation
*later*. Perhaps *instead* of doing it where we are at the moment.

But for now, doing what validation we *can* do in the place that the code
already has its validation, is an improvement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198760 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:58:28 +00:00

49 lines
1.3 KiB
ArmAsm

// RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t.err
// RUN: FileCheck --check-prefix=64 < %t.err %s
// RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t.err
// RUN: FileCheck --check-prefix=32 < %t.err %s
// rdar://8204588
// 64: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', or 'cmpq')
cmp $0, 0(%eax)
// 32: error: register %rax is only available in 64-bit mode
addl $0, 0(%rax)
// 32: test.s:8:2: error: invalid instruction mnemonic 'movi'
# 8 "test.s"
movi $8,%eax
movl 0(%rax), 0(%edx) // error: invalid operand for instruction
// 32: error: instruction requires: 64-bit mode
sysexitq
// rdar://10710167
// 64: error: expected scale expression
lea (%rsp, %rbp, $4), %rax
// rdar://10423777
// 64: error: base register is 64-bit, but index register is not
movq (%rsi,%ecx),%xmm0
// 64: error: invalid 16-bit base register
movl %eax,(%bp,%si)
// 32: error: scale factor in 16-bit address must be 1
movl %eax,(%bp,%si,2)
// 32: error: invalid 16-bit base register
movl %eax,(%cx)
// 32: error: invalid 16-bit base/index register combination
movl %eax,(%bp,%bx)
// 32: error: 16-bit memory operand may not include only index register
movl %eax,(,%bx)
// 32: error: invalid operand for instruction
outb al, 4