Tim Northover c077472250 ARM: add cyclone CPU with ZeroCycleZeroing feature. ... The Cyclone CPU is similar to swift for most LLVM purposes, but does have two preferred instructions for zeroing a VFP register. This teaches LLVM about them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205309 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-01 13:22:02 +00:00
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AArch64
ARM	ARM: add cyclone CPU with ZeroCycleZeroing feature.	2014-04-01 13:22:02 +00:00
ARM64	ARM64: add intrinsic for pmull (p64 x p64 = p128) operations.	2014-04-01 12:22:37 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Fixed issue with microMIPS JAL instruction.	2014-03-31 14:00:10 +00:00
MSP430
NVPTX	Fix for PR19099 - NVPTX produces invalid symbol names.	2014-03-31 15:56:26 +00:00
PowerPC	[PowerPC] Don't ever expand BUILD_VECTOR of v2i64 with shuffles	2014-03-31 17:48:16 +00:00
R600	R600: Compute masked bits for min and max	2014-03-31 19:35:33 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	[x86] Do not convert to cmp32 for Atom arch by Sergey Okunev	2014-04-01 08:13:07 +00:00
XCore