Zoran Jovanovic 70d1005bbd [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions ...

Differential Revision: http://reviews.llvm.org/D8800


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237697 91177308-0d34-0410-b5e6-96231b3b80d8

2015-05-19 14:12:55 +00:00

..

AArch64

AArch64: add BFC alias for the BFI/BFM instructions.

2015-04-30 18:28:58 +00:00

ARM

[DWARF] Add CIE header fields address_size and segment_size when generating dwarf-4

2015-05-12 15:25:08 +00:00

AsmParser

[MC] Use LShr for constant evaluation of ">>" on ELF/arm64--darwin.

2015-04-28 01:37:11 +00:00

COFF

Don't omit the constant when computing a cross-section relative relocation.

2015-05-14 01:10:41 +00:00

Disassembler

[mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions

2015-05-19 14:12:55 +00:00

ELF

[DWARF] Add CIE header fields address_size and segment_size when generating dwarf-4

2015-05-12 15:25:08 +00:00

Hexagon

Expand MUX instructions early on Hexagon

2015-03-31 13:35:12 +00:00

MachO

AArch64: work around ld64 bug more aggressively.

2015-05-18 22:07:20 +00:00

Markup

…

Mips

[mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions

2015-05-19 14:12:55 +00:00

PowerPC

[PPC64] Add vector pack/unpack support from ISA 2.07

2015-05-16 01:02:12 +00:00

R600

R600/SI: Add missing -mcpu=SI to assembler test

2015-04-23 19:33:55 +00:00

Sparc

Sparc: support the "set" synthetic instruction.

2015-05-18 16:43:33 +00:00

SystemZ

[SystemZ] Add z13 vector facility and MC support

2015-05-05 19:23:40 +00:00

X86

AVX-512: Added VBROADCASTF64X4, VBROADCASTF64X2, VBROADCASTI32X8, and other instructions from this set

2015-05-18 06:42:57 +00:00