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3f70e908c3
* msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188313 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
1.0 KiB
TableGen
35 lines
1.0 KiB
TableGen
//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def HasMSA : Predicate<"Subtarget.hasMSA()">,
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AssemblerPredicate<"FeatureMSA">;
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class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
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let Predicates = [HasMSA];
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let Inst{31-26} = 0b011110;
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}
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class PseudoMSA<dag outs, dag ins, list<dag> pattern,
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InstrItinClass itin = IIPseudo>:
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MipsPseudo<outs, ins, pattern, itin> {
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let Predicates = [HasMSA];
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}
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class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
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let Inst{25-23} = major;
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let Inst{22-21} = df;
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let Inst{5-0} = minor;
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}
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class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
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let Inst{25-23} = major;
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let Inst{22-21} = df;
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let Inst{5-0} = minor;
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}
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