mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-20 10:30:03 +00:00
cbd6ed4d6b
first before the chain.
e.g.
int X;
int foo(int x)
{
x += X + 37;
return x;
}
If chain operand is selected first, we would generate:
movl X, %eax
movl 4(%esp), %ecx
leal 37(%ecx,%eax), %eax
rather than
movl $37, %eax
addl 4(%esp), %eax
addl X, %eax
which does not require %ecx. (Due to ADD32rm not matching.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24673 91177308-0d34-0410-b5e6-96231b3b80d8
409 lines
13 KiB
C++
409 lines
13 KiB
C++
//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Evan Cheng and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a DAG pattern matching instruction selector for X86,
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// converting from a legalized dag to a X86 dag.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86Subtarget.h"
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#include "X86ISelLowering.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Pattern Matcher Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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/// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
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/// SDOperand's instead of register numbers for the leaves of the matched
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/// tree.
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struct X86ISelAddressMode {
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enum {
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RegBase,
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FrameIndexBase,
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ConstantPoolBase
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} BaseType;
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struct { // This is really a union, discriminated by BaseType!
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SDOperand Reg;
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int FrameIndex;
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} Base;
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unsigned Scale;
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SDOperand IndexReg;
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unsigned Disp;
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GlobalValue *GV;
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X86ISelAddressMode()
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: BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0) {
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}
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};
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}
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namespace {
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Statistic<>
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NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
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//===--------------------------------------------------------------------===//
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/// ISel - X86 specific code to select X86 machine instructions for
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/// SelectionDAG operations.
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///
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class X86DAGToDAGISel : public SelectionDAGISel {
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/// ContainsFPCode - Every instruction we select that uses or defines a FP
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/// register should set this to true.
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bool ContainsFPCode;
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/// X86Lowering - This object fully describes how to lower LLVM code to an
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/// X86-specific SelectionDAG.
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X86TargetLowering X86Lowering;
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/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const X86Subtarget *Subtarget;
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public:
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X86DAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(X86Lowering), X86Lowering(TM) {
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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}
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virtual const char *getPassName() const {
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return "X86 DAG->DAG Instruction Selection";
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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// Include the pieces autogenerated from the target description.
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#include "X86GenDAGISel.inc"
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private:
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SDOperand Select(SDOperand N);
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bool MatchAddress(SDOperand N, X86ISelAddressMode &AM);
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bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp);
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bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp);
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/// getI8Imm - Return a target constant with the specified value, of type
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/// i8.
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inline SDOperand getI8Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i8);
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}
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/// getI16Imm - Return a target constant with the specified value, of type
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/// i16.
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inline SDOperand getI16Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i16);
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}
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDOperand getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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};
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}
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/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
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/// when it has created a SelectionDAG for us to codegen.
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void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Codegen the basic block.
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DAG.setRoot(Select(DAG.getRoot()));
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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/// FIXME: copied from X86ISelPattern.cpp
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/// MatchAddress - Add the specified node to the specified addressing mode,
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/// returning true if it cannot be done. This just pattern matches for the
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/// addressing mode
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bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
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switch (N.getOpcode()) {
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default: break;
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case ISD::FrameIndex:
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if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
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AM.BaseType = X86ISelAddressMode::FrameIndexBase;
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AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
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return false;
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}
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break;
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case ISD::ConstantPool:
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if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N)) {
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AM.BaseType = X86ISelAddressMode::ConstantPoolBase;
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AM.Base.Reg = CurDAG->getTargetConstantPool(CP->get(), MVT::i32);
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return false;
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}
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}
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break;
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case ISD::GlobalAddress:
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if (AM.GV == 0) {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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// For Darwin, external and weak symbols are indirect, so we want to load
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// the value at address GV, not the value of GV itself. This means that
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// the GlobalAddress must be in the base or index register of the address,
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// not the GV offset field.
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if (Subtarget->getIndirectExternAndWeakGlobals() &&
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(GV->hasWeakLinkage() || GV->isExternal())) {
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break;
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} else {
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AM.GV = GV;
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return false;
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}
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}
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break;
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case ISD::Constant:
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AM.Disp += cast<ConstantSDNode>(N)->getValue();
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return false;
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case ISD::SHL:
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if (AM.IndexReg.Val == 0 && AM.Scale == 1)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
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unsigned Val = CN->getValue();
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if (Val == 1 || Val == 2 || Val == 3) {
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AM.Scale = 1 << Val;
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SDOperand ShVal = N.Val->getOperand(0);
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// Okay, we know that we have a scale by now. However, if the scaled
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// value is an add of something and a constant, we can fold the
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// constant into the disp field here.
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if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
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isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
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AM.IndexReg = ShVal.Val->getOperand(0);
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ConstantSDNode *AddVal =
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cast<ConstantSDNode>(ShVal.Val->getOperand(1));
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AM.Disp += AddVal->getValue() << Val;
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} else {
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AM.IndexReg = ShVal;
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}
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return false;
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}
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}
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break;
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case ISD::MUL:
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// X*[3,5,9] -> X+X*[2,4,8]
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if (AM.IndexReg.Val == 0 && AM.BaseType == X86ISelAddressMode::RegBase &&
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AM.Base.Reg.Val == 0)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
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if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
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AM.Scale = unsigned(CN->getValue())-1;
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SDOperand MulVal = N.Val->getOperand(0);
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SDOperand Reg;
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// Okay, we know that we have a scale by now. However, if the scaled
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// value is an add of something and a constant, we can fold the
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// constant into the disp field here.
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if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
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isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
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Reg = MulVal.Val->getOperand(0);
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ConstantSDNode *AddVal =
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cast<ConstantSDNode>(MulVal.Val->getOperand(1));
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AM.Disp += AddVal->getValue() * CN->getValue();
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} else {
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Reg = N.Val->getOperand(0);
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}
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AM.IndexReg = AM.Base.Reg = Reg;
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return false;
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}
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break;
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case ISD::ADD: {
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X86ISelAddressMode Backup = AM;
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if (!MatchAddress(N.Val->getOperand(0), AM) &&
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!MatchAddress(N.Val->getOperand(1), AM))
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return false;
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AM = Backup;
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if (!MatchAddress(N.Val->getOperand(1), AM) &&
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!MatchAddress(N.Val->getOperand(0), AM))
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return false;
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AM = Backup;
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break;
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}
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}
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// Is the base register already occupied?
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if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
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// If so, check to see if the scale index register is set.
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if (AM.IndexReg.Val == 0) {
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AM.IndexReg = N;
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AM.Scale = 1;
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return false;
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}
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// Otherwise, we cannot select it.
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return true;
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}
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// Default, generate it as a register.
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AM.BaseType = X86ISelAddressMode::RegBase;
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AM.Base.Reg = N;
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return false;
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}
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/// SelectAddr - returns true if it is able pattern match an addressing mode.
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/// It returns the operands which make up the maximal addressing mode it can
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/// match by reference.
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bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp) {
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X86ISelAddressMode AM;
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if (!MatchAddress(N, AM)) {
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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if (AM.Base.Reg.Val)
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AM.Base.Reg = Select(AM.Base.Reg);
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else
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AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
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}
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if (AM.IndexReg.Val)
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AM.IndexReg = Select(AM.IndexReg);
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else
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AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
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Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
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CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) : AM.Base.Reg;
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Scale = getI8Imm (AM.Scale);
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Index = AM.IndexReg;
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Disp = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
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: getI32Imm(AM.Disp);
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return true;
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}
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return false;
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}
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static bool isRegister0(SDOperand Op)
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{
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if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op))
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return (R->getReg() == 0);
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return false;
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}
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/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
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/// mode it matches can be cost effectively emitted as an LEA instruction.
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/// For X86, it always is unless it's just a (Reg + const).
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bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp) {
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if (SelectAddr(N, Base, Scale, Index, Disp)) {
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if (!isRegister0(Base)) {
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unsigned Complexity = 0;
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if ((unsigned)cast<ConstantSDNode>(Scale)->getValue() > 1)
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Complexity++;
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if (!isRegister0(Index))
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Complexity++;
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Disp)) {
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if (!CN->isNullValue()) Complexity++;
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} else {
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Complexity++;
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}
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return (Complexity > 1);
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}
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return true;
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} else {
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return false;
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}
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}
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SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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MVT::ValueType OpVT = N->getValueType(0);
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unsigned Opc;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END)
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return Op; // Already selected.
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switch (N->getOpcode()) {
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default: break;
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case ISD::SHL:
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
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if (CN->getValue() == 1) {
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// X = SHL Y, 1 -> X = ADD Y, Y
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switch (OpVT) {
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default: assert(0 && "Cannot shift this type!");
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case MVT::i8: Opc = X86::ADD8rr; break;
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case MVT::i16: Opc = X86::ADD16rr; break;
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case MVT::i32: Opc = X86::ADD32rr; break;
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}
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SDOperand Tmp0 = Select(N->getOperand(0));
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0, Tmp0);
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}
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}
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break;
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case ISD::RET: {
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SDOperand Chain = N->getOperand(0); // Token chain.
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unsigned NumOps = N->getNumOperands();
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// Note: A bit of a hack / optimization... Try to delay chain selection
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// as much as possible. So it's more likely it has already been selected
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// for a real use.
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switch (NumOps) {
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default:
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assert(0 && "Unknown return instruction!");
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case 3:
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Chain = Select(Chain);
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assert(0 && "Not yet handled return instruction!");
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break;
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case 2: {
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SDOperand Val = Select(N->getOperand(1));
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Chain = Select(Chain);
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switch (N->getOperand(1).getValueType()) {
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default:
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assert(0 && "All other types should have been promoted!!");
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case MVT::i32:
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Chain = CurDAG->getCopyToReg(Chain, X86::EAX, Val);
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break;
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case MVT::f32:
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case MVT::f64:
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assert(0 && "Not yet handled return instruction!");
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break;
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}
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}
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case 1:
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Chain = Select(Chain);
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break;
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}
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if (X86Lowering.getBytesToPopOnReturn() == 0)
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return CurDAG->SelectNodeTo(N, X86::RET, MVT::Other, Chain);
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else
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return CurDAG->SelectNodeTo(N, X86::RET, MVT::Other,
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getI16Imm(X86Lowering.getBytesToPopOnReturn()),
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Chain);
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}
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}
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return SelectCode(Op);
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}
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/// createX86ISelDag - This pass converts a legalized DAG into a
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/// X86-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createX86ISelDag(TargetMachine &TM) {
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return new X86DAGToDAGISel(TM);
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}
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