Jakob Stoklund Olesen 083b48af14 Add ADD and SUB to the predicable ARM instructions. ... It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162061 91177308-0d34-0410-b5e6-96231b3b80d8		2012-08-16 23:21:55 +00:00
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Analysis	Set the branch probability of branching to the 'normal' destination of an invoke	2012-08-15 12:22:35 +00:00
Archive
AsmParser
Bitcode
CodeGen	Add an MCID::Select flag and TII hooks for optimizing selects.	2012-08-16 23:11:47 +00:00
DebugInfo
ExecutionEngine	Fixed a problem in the JIT memory allocator where	2012-08-15 20:53:52 +00:00
Linker
MC	When emitting the PC range in an FDE, use the same data encoding for both ends	2012-08-12 08:09:45 +00:00
Object
Support	Properly test the LLVM_USE_RVALUE_REFERENCES macro.	2012-08-15 19:16:27 +00:00
TableGen
Target	Add ADD and SUB to the predicable ARM instructions.	2012-08-16 23:21:55 +00:00
Transforms	Teach GVN to reason about edges dominating uses. This allows it to handle cases	2012-08-16 15:09:43 +00:00
VMCore	Teach GVN to reason about edges dominating uses. This allows it to handle cases	2012-08-16 15:09:43 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile