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https://github.com/c64scene-ar/llvm-6502.git
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c67c18fd23
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22918 91177308-0d34-0410-b5e6-96231b3b80d8
298 lines
10 KiB
C++
298 lines
10 KiB
C++
//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class wrap target description classes used by the various code
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// generation TableGen backends. This makes it easier to access the data and
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// provides a single place that needs to check it for validity. All of these
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// classes throw exceptions on error conditions.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<unsigned>
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AsmWriterNum("asmwriternum", cl::init(0),
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cl::desc("Make -gen-asm-writer emit assembly writer #N"));
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/// getValueType - Return the MCV::ValueType that the specified TableGen record
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/// corresponds to.
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MVT::ValueType llvm::getValueType(Record *Rec) {
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return (MVT::ValueType)Rec->getValueAsInt("Value");
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}
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std::string llvm::getName(MVT::ValueType T) {
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switch (T) {
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case MVT::Other: return "UNKNOWN";
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case MVT::i1: return "i1";
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case MVT::i8: return "i8";
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case MVT::i16: return "i16";
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case MVT::i32: return "i32";
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case MVT::i64: return "i64";
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case MVT::i128: return "i128";
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case MVT::f32: return "f32";
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case MVT::f64: return "f64";
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case MVT::f80: return "f80";
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case MVT::f128: return "f128";
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case MVT::isVoid:return "void";
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default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
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}
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}
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std::string llvm::getEnumName(MVT::ValueType T) {
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switch (T) {
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case MVT::Other: return "Other";
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case MVT::i1: return "i1";
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case MVT::i8: return "i8";
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case MVT::i16: return "i16";
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case MVT::i32: return "i32";
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case MVT::i64: return "i64";
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case MVT::i128: return "i128";
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case MVT::f32: return "f32";
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case MVT::f64: return "f64";
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case MVT::f80: return "f80";
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case MVT::f128: return "f128";
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case MVT::isVoid:return "isVoid";
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default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
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}
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}
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std::ostream &llvm::operator<<(std::ostream &OS, MVT::ValueType T) {
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return OS << getName(T);
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}
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/// getTarget - Return the current instance of the Target class.
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///
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CodeGenTarget::CodeGenTarget() : PointerType(MVT::Other) {
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std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
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if (Targets.size() == 0)
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throw std::string("ERROR: No 'Target' subclasses defined!");
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if (Targets.size() != 1)
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throw std::string("ERROR: Multiple subclasses of Target defined!");
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TargetRec = Targets[0];
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// Read in all of the CalleeSavedRegisters...
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ListInit *LI = TargetRec->getValueAsListInit("CalleeSavedRegisters");
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for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
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if (DefInit *DI = dynamic_cast<DefInit*>(LI->getElement(i)))
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CalleeSavedRegisters.push_back(DI->getDef());
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else
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throw "Target: " + TargetRec->getName() +
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" expected register definition in CalleeSavedRegisters list!";
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PointerType = getValueType(TargetRec->getValueAsDef("PointerType"));
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}
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const std::string &CodeGenTarget::getName() const {
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return TargetRec->getName();
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}
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Record *CodeGenTarget::getInstructionSet() const {
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return TargetRec->getValueAsDef("InstructionSet");
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}
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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Record *CodeGenTarget::getAsmWriter() const {
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ListInit *LI = TargetRec->getValueAsListInit("AssemblyWriters");
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if (AsmWriterNum >= LI->getSize())
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throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
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DefInit *DI = dynamic_cast<DefInit*>(LI->getElement(AsmWriterNum));
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if (!DI) throw std::string("AssemblyWriter list should be a list of defs!");
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return DI->getDef();
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}
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void CodeGenTarget::ReadRegisters() const {
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std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
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if (Regs.empty())
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throw std::string("No 'Register' subclasses defined!");
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Registers.reserve(Regs.size());
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Registers.assign(Regs.begin(), Regs.end());
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}
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CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
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DeclaredSpillSize = R->getValueAsInt("SpillSize");
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DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
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}
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const std::string &CodeGenRegister::getName() const {
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return TheDef->getName();
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}
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void CodeGenTarget::ReadRegisterClasses() const {
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std::vector<Record*> RegClasses =
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Records.getAllDerivedDefinitions("RegisterClass");
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if (RegClasses.empty())
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throw std::string("No 'RegisterClass' subclasses defined!");
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RegisterClasses.reserve(RegClasses.size());
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RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
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}
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CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
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// Rename anonymous register classes.
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if (R->getName().size() > 9 && R->getName()[9] == '.') {
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static unsigned AnonCounter = 0;
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R->setName("AnonRegClass_"+utostr(AnonCounter++));
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}
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Namespace = R->getValueAsString("Namespace");
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SpillSize = R->getValueAsInt("Size");
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SpillAlignment = R->getValueAsInt("Alignment");
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if (CodeInit *CI = dynamic_cast<CodeInit*>(R->getValueInit("Methods")))
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MethodDefinitions = CI->getValue();
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else
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throw "Expected 'code' fragment for 'Methods' value in register class '"+
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getName() + "'!";
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ListInit *RegList = R->getValueAsListInit("MemberList");
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for (unsigned i = 0, e = RegList->getSize(); i != e; ++i) {
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DefInit *RegDef = dynamic_cast<DefInit*>(RegList->getElement(i));
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if (!RegDef) throw "Register class member is not a record!";
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Record *Reg = RegDef->getDef();
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if (!Reg->isSubClassOf("Register"))
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throw "Register Class member '" + Reg->getName() +
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"' does not derive from the Register class!";
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Elements.push_back(Reg);
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}
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}
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const std::string &CodeGenRegisterClass::getName() const {
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return TheDef->getName();
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}
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void CodeGenTarget::ReadInstructions() const {
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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if (Insts.empty())
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throw std::string("No 'Instruction' subclasses defined!");
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std::string InstFormatName =
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getAsmWriter()->getValueAsString("InstFormatName");
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for (unsigned i = 0, e = Insts.size(); i != e; ++i) {
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std::string AsmStr = Insts[i]->getValueAsString(InstFormatName);
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Instructions.insert(std::make_pair(Insts[i]->getName(),
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CodeGenInstruction(Insts[i], AsmStr)));
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}
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}
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/// getPHIInstruction - Return the designated PHI instruction.
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///
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const CodeGenInstruction &CodeGenTarget::getPHIInstruction() const {
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Record *PHI = getInstructionSet()->getValueAsDef("PHIInst");
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std::map<std::string, CodeGenInstruction>::const_iterator I =
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getInstructions().find(PHI->getName());
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if (I == Instructions.end())
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throw "Could not find PHI instruction named '" + PHI->getName() + "'!";
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return I->second;
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}
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/// getInstructionsByEnumValue - Return all of the instructions defined by the
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/// target, ordered by their enum value.
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void CodeGenTarget::
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getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
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&NumberedInstructions) {
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// Print out the rest of the instructions now.
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unsigned i = 0;
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const CodeGenInstruction *PHI = &getPHIInstruction();
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NumberedInstructions.push_back(PHI);
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for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
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if (&II->second != PHI)
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NumberedInstructions.push_back(&II->second);
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}
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/// isLittleEndianEncoding - Return whether this target encodes its instruction
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/// in little-endian format, i.e. bits laid out in the order [0..n]
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///
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bool CodeGenTarget::isLittleEndianEncoding() const {
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return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
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}
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CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
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: TheDef(R), AsmString(AsmStr) {
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Name = R->getValueAsString("Name");
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Namespace = R->getValueAsString("Namespace");
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isReturn = R->getValueAsBit("isReturn");
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isBranch = R->getValueAsBit("isBranch");
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isBarrier = R->getValueAsBit("isBarrier");
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isCall = R->getValueAsBit("isCall");
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isLoad = R->getValueAsBit("isLoad");
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isStore = R->getValueAsBit("isStore");
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isTwoAddress = R->getValueAsBit("isTwoAddress");
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isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
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isCommutable = R->getValueAsBit("isCommutable");
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isTerminator = R->getValueAsBit("isTerminator");
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hasDelaySlot = R->getValueAsBit("hasDelaySlot");
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hasVariableNumberOfOperands = false;
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try {
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DagInit *DI = R->getValueAsDag("OperandList");
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unsigned MIOperandNo = 0;
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for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i)
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if (DefInit *Arg = dynamic_cast<DefInit*>(DI->getArg(i))) {
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Record *Rec = Arg->getDef();
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MVT::ValueType Ty;
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std::string PrintMethod = "printOperand";
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unsigned NumOps = 1;
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if (Rec->isSubClassOf("RegisterClass")) {
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Ty = getValueType(Rec->getValueAsDef("RegType"));
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} else if (Rec->isSubClassOf("Operand")) {
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Ty = getValueType(Rec->getValueAsDef("Type"));
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PrintMethod = Rec->getValueAsString("PrintMethod");
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NumOps = Rec->getValueAsInt("NumMIOperands");
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} else if (Rec->getName() == "variable_ops") {
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hasVariableNumberOfOperands = true;
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continue;
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} else
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throw "Unknown operand class '" + Rec->getName() +
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"' in instruction '" + R->getName() + "' instruction!";
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OperandList.push_back(OperandInfo(Rec, Ty, DI->getArgName(i),
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PrintMethod, MIOperandNo, NumOps));
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MIOperandNo += NumOps;
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} else {
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throw "Illegal operand for the '" + R->getName() + "' instruction!";
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}
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} catch (...) {
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// Error parsing operands list, just ignore it.
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AsmString.clear();
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OperandList.clear();
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}
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}
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/// getOperandNamed - Return the index of the operand with the specified
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/// non-empty name. If the instruction does not have an operand with the
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/// specified name, throw an exception.
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///
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unsigned CodeGenInstruction::getOperandNamed(const std::string &Name) const {
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assert(!Name.empty() && "Cannot search for operand with no name!");
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for (unsigned i = 0, e = OperandList.size(); i != e; ++i)
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if (OperandList[i].Name == Name) return i;
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throw "Instruction '" + TheDef->getName() +
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"' does not have an operand named '$" + Name + "'!";
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}
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