mirror of
https://github.com/c64scene-ar/llvm-6502.git
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01c0dd1be3
a failure if run on an Intel Atom with post RA instruction scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155587 91177308-0d34-0410-b5e6-96231b3b80d8
140 lines
4.3 KiB
LLVM
140 lines
4.3 KiB
LLVM
; RUN: llc < %s -mcpu=generic -march=x86 | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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define void @func(i32 %argc, i8** %argv) nounwind {
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entry:
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%argc.addr = alloca i32 ; <i32*> [#uses=1]
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%argv.addr = alloca i8** ; <i8***> [#uses=1]
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%val1 = alloca i32 ; <i32*> [#uses=2]
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%val2 = alloca i32 ; <i32*> [#uses=15]
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%andt = alloca i32 ; <i32*> [#uses=2]
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%ort = alloca i32 ; <i32*> [#uses=2]
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%xort = alloca i32 ; <i32*> [#uses=2]
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%old = alloca i32 ; <i32*> [#uses=18]
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%temp = alloca i32 ; <i32*> [#uses=2]
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%temp64 = alloca i64
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store i32 %argc, i32* %argc.addr
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store i8** %argv, i8*** %argv.addr
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store i32 0, i32* %val1
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store i32 31, i32* %val2
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store i32 3855, i32* %andt
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store i32 3855, i32* %ort
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store i32 3855, i32* %xort
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store i32 4, i32* %temp
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%tmp = load i32* %temp
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; CHECK: lock
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; CHECK: xaddl
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%0 = atomicrmw add i32* %val1, i32 %tmp monotonic
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store i32 %0, i32* %old
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; CHECK: lock
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; CHECK: xaddl
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%1 = atomicrmw sub i32* %val2, i32 30 monotonic
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store i32 %1, i32* %old
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; CHECK: lock
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; CHECK: xaddl
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%2 = atomicrmw add i32* %val2, i32 1 monotonic
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store i32 %2, i32* %old
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; CHECK: lock
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; CHECK: xaddl
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%3 = atomicrmw sub i32* %val2, i32 1 monotonic
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store i32 %3, i32* %old
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; CHECK: andl
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; CHECK: lock
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; CHECK: cmpxchgl
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%4 = atomicrmw and i32* %andt, i32 4080 monotonic
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store i32 %4, i32* %old
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; CHECK: orl
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; CHECK: lock
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; CHECK: cmpxchgl
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%5 = atomicrmw or i32* %ort, i32 4080 monotonic
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store i32 %5, i32* %old
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; CHECK: xorl
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; CHECK: lock
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; CHECK: cmpxchgl
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%6 = atomicrmw xor i32* %xort, i32 4080 monotonic
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store i32 %6, i32* %old
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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%7 = atomicrmw min i32* %val2, i32 16 monotonic
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store i32 %7, i32* %old
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%neg = sub i32 0, 1 ; <i32> [#uses=1]
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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%8 = atomicrmw min i32* %val2, i32 %neg monotonic
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store i32 %8, i32* %old
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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%9 = atomicrmw max i32* %val2, i32 1 monotonic
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store i32 %9, i32* %old
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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%10 = atomicrmw max i32* %val2, i32 0 monotonic
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store i32 %10, i32* %old
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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%11 = atomicrmw umax i32* %val2, i32 65535 monotonic
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store i32 %11, i32* %old
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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%12 = atomicrmw umax i32* %val2, i32 10 monotonic
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store i32 %12, i32* %old
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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%13 = atomicrmw umin i32* %val2, i32 1 monotonic
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store i32 %13, i32* %old
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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%14 = atomicrmw umin i32* %val2, i32 10 monotonic
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store i32 %14, i32* %old
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; CHECK: xchgl %{{.*}}, {{.*}}(%esp)
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%15 = atomicrmw xchg i32* %val2, i32 1976 monotonic
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store i32 %15, i32* %old
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%neg1 = sub i32 0, 10 ; <i32> [#uses=1]
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; CHECK: lock
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; CHECK: cmpxchgl
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%16 = cmpxchg i32* %val2, i32 %neg1, i32 1 monotonic
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store i32 %16, i32* %old
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; CHECK: lock
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; CHECK: cmpxchgl
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%17 = cmpxchg i32* %val2, i32 1976, i32 1 monotonic
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store i32 %17, i32* %old
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; CHECK: movl $1401, %[[R17mask:[a-z]*]]
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; CHECK: movl [[R17atomic:.*]], %eax
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; CHECK: movl %eax, %[[R17newval:[a-z]*]]
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; CHECK: andl %[[R17mask]], %[[R17newval]]
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; CHECK: notl %[[R17newval]]
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; CHECK: lock
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; CHECK: cmpxchgl %[[R17newval]], [[R17atomic]]
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; CHECK: jne
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; CHECK: movl %eax,
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%18 = atomicrmw nand i32* %val2, i32 1401 monotonic
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store i32 %18, i32* %old
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; CHECK: andl
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; CHECK: andl
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; CHECK: notl
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; CHECK: notl
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; CHECK: lock
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; CHECK: cmpxchg8b
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%19 = atomicrmw nand i64* %temp64, i64 17361641481138401520 monotonic
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store i64 %19, i64* %temp64
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ret void
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}
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define void @test2(i32 addrspace(256)* nocapture %P) nounwind {
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entry:
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; CHECK: lock
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; CHECK: cmpxchgl %{{.*}}, %gs:(%{{.*}})
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%0 = cmpxchg i32 addrspace(256)* %P, i32 0, i32 1 monotonic
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ret void
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}
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