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9b75b37375
argument instead of taking the SelectionDAG's TargetMachine. This is needed for some upcoming scheduler changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59055 91177308-0d34-0410-b5e6-96231b3b80d8
1182 lines
44 KiB
C++
1182 lines
44 KiB
C++
//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the SelectionDAGISel class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "isel"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "SelectionDAGBuild.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Constants.h"
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#include "llvm/CallingConv.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/InlineAsm.h"
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/IntrinsicInst.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/GCStrategy.h"
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#include "llvm/CodeGen/GCMetadata.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/Timer.h"
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#include <algorithm>
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using namespace llvm;
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static cl::opt<bool>
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EnableValueProp("enable-value-prop", cl::Hidden);
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static cl::opt<bool>
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DisableLegalizeTypes("disable-legalize-types", cl::Hidden);
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#ifndef NDEBUG
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static cl::opt<bool>
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EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
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cl::desc("Enable verbose messages in the \"fast\" "
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"instruction selector"));
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static cl::opt<bool>
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EnableFastISelAbort("fast-isel-abort", cl::Hidden,
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cl::desc("Enable abort calls when \"fast\" instruction fails"));
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#else
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static const bool EnableFastISelVerbose = false,
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EnableFastISelAbort = false;
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#endif
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static cl::opt<bool>
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SchedLiveInCopies("schedule-livein-copies",
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cl::desc("Schedule copies of livein registers"),
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cl::init(false));
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#ifndef NDEBUG
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static cl::opt<bool>
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ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
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cl::desc("Pop up a window to show dags before the first "
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"dag combine pass"));
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static cl::opt<bool>
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ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
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cl::desc("Pop up a window to show dags before legalize types"));
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static cl::opt<bool>
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ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
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cl::desc("Pop up a window to show dags before legalize"));
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static cl::opt<bool>
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ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
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cl::desc("Pop up a window to show dags before the second "
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"dag combine pass"));
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static cl::opt<bool>
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ViewISelDAGs("view-isel-dags", cl::Hidden,
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cl::desc("Pop up a window to show isel dags as they are selected"));
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static cl::opt<bool>
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ViewSchedDAGs("view-sched-dags", cl::Hidden,
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cl::desc("Pop up a window to show sched dags as they are processed"));
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static cl::opt<bool>
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ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
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cl::desc("Pop up a window to show SUnit dags after they are processed"));
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#else
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static const bool ViewDAGCombine1 = false,
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ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
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ViewDAGCombine2 = false,
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ViewISelDAGs = false, ViewSchedDAGs = false,
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ViewSUnitDAGs = false;
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#endif
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//===---------------------------------------------------------------------===//
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///
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/// RegisterScheduler class - Track the registration of instruction schedulers.
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///
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//===---------------------------------------------------------------------===//
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MachinePassRegistry RegisterScheduler::Registry;
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//===---------------------------------------------------------------------===//
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///
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/// ISHeuristic command line option for instruction schedulers.
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///
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//===---------------------------------------------------------------------===//
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static cl::opt<RegisterScheduler::FunctionPassCtor, false,
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RegisterPassParser<RegisterScheduler> >
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ISHeuristic("pre-RA-sched",
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cl::init(&createDefaultScheduler),
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cl::desc("Instruction schedulers available (before register"
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" allocation):"));
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static RegisterScheduler
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defaultListDAGScheduler("default", "Best scheduler for the target",
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createDefaultScheduler);
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namespace llvm {
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//===--------------------------------------------------------------------===//
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/// createDefaultScheduler - This creates an instruction scheduler appropriate
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/// for the target.
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ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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const TargetMachine *TM,
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MachineBasicBlock *BB,
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bool Fast) {
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TargetLowering &TLI = IS->getTargetLowering();
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if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
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return createTDListDAGScheduler(IS, DAG, TM, BB, Fast);
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} else {
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assert(TLI.getSchedulingPreference() ==
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TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
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return createBURRListDAGScheduler(IS, DAG, TM, BB, Fast);
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}
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}
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}
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// EmitInstrWithCustomInserter - This method should be implemented by targets
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// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
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// instructions are special in various ways, which require special support to
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// insert. The specified MachineInstr is created but not inserted into any
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// basic blocks, and the scheduler passes ownership of it to this method.
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MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) {
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cerr << "If a target marks an instruction with "
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<< "'usesCustomDAGSchedInserter', it must implement "
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<< "TargetLowering::EmitInstrWithCustomInserter!\n";
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abort();
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return 0;
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}
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/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
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/// physical register has only a single copy use, then coalesced the copy
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/// if possible.
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static void EmitLiveInCopy(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &InsertPos,
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unsigned VirtReg, unsigned PhysReg,
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const TargetRegisterClass *RC,
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DenseMap<MachineInstr*, unsigned> &CopyRegMap,
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const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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const TargetInstrInfo &TII) {
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unsigned NumUses = 0;
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MachineInstr *UseMI = NULL;
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for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
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UE = MRI.use_end(); UI != UE; ++UI) {
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UseMI = &*UI;
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if (++NumUses > 1)
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break;
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}
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// If the number of uses is not one, or the use is not a move instruction,
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// don't coalesce. Also, only coalesce away a virtual register to virtual
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// register copy.
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bool Coalesced = false;
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unsigned SrcReg, DstReg;
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if (NumUses == 1 &&
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TII.isMoveInstr(*UseMI, SrcReg, DstReg) &&
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TargetRegisterInfo::isVirtualRegister(DstReg)) {
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VirtReg = DstReg;
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Coalesced = true;
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}
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// Now find an ideal location to insert the copy.
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MachineBasicBlock::iterator Pos = InsertPos;
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while (Pos != MBB->begin()) {
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MachineInstr *PrevMI = prior(Pos);
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DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
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// copyRegToReg might emit multiple instructions to do a copy.
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unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
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if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
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// This is what the BB looks like right now:
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// r1024 = mov r0
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// ...
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// r1 = mov r1024
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//
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// We want to insert "r1025 = mov r1". Inserting this copy below the
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// move to r1024 makes it impossible for that move to be coalesced.
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//
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// r1025 = mov r1
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// r1024 = mov r0
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// ...
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// r1 = mov 1024
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// r2 = mov 1025
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break; // Woot! Found a good location.
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--Pos;
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}
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TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
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CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
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if (Coalesced) {
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if (&*InsertPos == UseMI) ++InsertPos;
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MBB->erase(UseMI);
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}
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}
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/// EmitLiveInCopies - If this is the first basic block in the function,
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/// and if it has live ins that need to be copied into vregs, emit the
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/// copies into the block.
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static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
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const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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const TargetInstrInfo &TII) {
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if (SchedLiveInCopies) {
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// Emit the copies at a heuristically-determined location in the block.
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DenseMap<MachineInstr*, unsigned> CopyRegMap;
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MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
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for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
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E = MRI.livein_end(); LI != E; ++LI)
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if (LI->second) {
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const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
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EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
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RC, CopyRegMap, MRI, TRI, TII);
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}
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} else {
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// Emit the copies into the top of the block.
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for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
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E = MRI.livein_end(); LI != E; ++LI)
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if (LI->second) {
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const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
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TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
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LI->second, LI->first, RC, RC);
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// SelectionDAGISel code
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//===----------------------------------------------------------------------===//
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SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) :
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FunctionPass(&ID), TLI(tli),
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FuncInfo(new FunctionLoweringInfo(TLI)),
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CurDAG(new SelectionDAG(TLI, *FuncInfo)),
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SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)),
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GFI(),
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Fast(fast),
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DAGSize(0)
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{}
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SelectionDAGISel::~SelectionDAGISel() {
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delete SDL;
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delete CurDAG;
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delete FuncInfo;
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}
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unsigned SelectionDAGISel::MakeReg(MVT VT) {
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return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
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}
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void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<AliasAnalysis>();
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AU.addRequired<GCModuleInfo>();
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AU.setPreservesAll();
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}
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bool SelectionDAGISel::runOnFunction(Function &Fn) {
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// Do some sanity-checking on the command-line options.
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assert((!EnableFastISelVerbose || EnableFastISel) &&
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"-fast-isel-verbose requires -fast-isel");
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assert((!EnableFastISelAbort || EnableFastISel) &&
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"-fast-isel-abort requires -fast-isel");
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// Get alias analysis for load/store combining.
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AA = &getAnalysis<AliasAnalysis>();
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TargetMachine &TM = TLI.getTargetMachine();
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MachineFunction &MF = MachineFunction::construct(&Fn, TM);
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
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if (MF.getFunction()->hasGC())
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GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction());
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else
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GFI = 0;
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RegInfo = &MF.getRegInfo();
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DOUT << "\n\n\n=== " << Fn.getName() << "\n";
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FuncInfo->set(Fn, MF, EnableFastISel);
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MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>();
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CurDAG->init(MF, MMI);
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SDL->init(GFI, *AA);
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for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
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if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
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// Mark landing pad.
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FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
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SelectAllBasicBlocks(Fn, MF, MMI, TII);
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// If the first basic block in the function has live ins that need to be
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// copied into vregs, emit the copies into the top of the block before
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// emitting the code for the block.
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EmitLiveInCopies(MF.begin(), MRI, TRI, TII);
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// Add function live-ins to entry block live-in set.
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for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
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E = RegInfo->livein_end(); I != E; ++I)
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MF.begin()->addLiveIn(I->first);
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#ifndef NDEBUG
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assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
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"Not all catch info was assigned to a landing pad!");
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#endif
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FuncInfo->clear();
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return true;
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}
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static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
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MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
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for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
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if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) {
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// Apply the catch info to DestBB.
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AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]);
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#ifndef NDEBUG
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if (!FLI.MBBMap[SrcBB]->isLandingPad())
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FLI.CatchInfoFound.insert(EHSel);
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#endif
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}
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}
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/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
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/// whether object offset >= 0.
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static bool
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IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
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if (!isa<FrameIndexSDNode>(Op)) return false;
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FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
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int FrameIdx = FrameIdxNode->getIndex();
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return MFI->isFixedObjectIndex(FrameIdx) &&
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MFI->getObjectOffset(FrameIdx) >= 0;
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}
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/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
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/// possibly be overwritten when lowering the outgoing arguments in a tail
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/// call. Currently the implementation of this call is very conservative and
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/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
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/// virtual registers would be overwritten by direct lowering.
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static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
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MachineFrameInfo * MFI) {
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RegisterSDNode * OpReg = NULL;
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if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
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(Op.getOpcode()== ISD::CopyFromReg &&
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(OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
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(OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
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(Op.getOpcode() == ISD::LOAD &&
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IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
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(Op.getOpcode() == ISD::MERGE_VALUES &&
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Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD &&
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IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()).
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getOperand(1))))
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return true;
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return false;
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}
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/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
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/// DAG and fixes their tailcall attribute operand.
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static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
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TargetLowering& TLI) {
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SDNode * Ret = NULL;
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SDValue Terminator = DAG.getRoot();
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// Find RET node.
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if (Terminator.getOpcode() == ISD::RET) {
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Ret = Terminator.getNode();
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}
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// Fix tail call attribute of CALL nodes.
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for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
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BI = DAG.allnodes_end(); BI != BE; ) {
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--BI;
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if (CallSDNode *TheCall = dyn_cast<CallSDNode>(BI)) {
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SDValue OpRet(Ret, 0);
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SDValue OpCall(BI, 0);
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bool isMarkedTailCall = TheCall->isTailCall();
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// If CALL node has tail call attribute set to true and the call is not
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// eligible (no RET or the target rejects) the attribute is fixed to
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// false. The TargetLowering::IsEligibleForTailCallOptimization function
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// must correctly identify tail call optimizable calls.
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if (!isMarkedTailCall) continue;
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if (Ret==NULL ||
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!TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) {
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// Not eligible. Mark CALL node as non tail call. Note that we
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// can modify the call node in place since calls are not CSE'd.
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TheCall->setNotTailCall();
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} else {
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// Look for tail call clobbered arguments. Emit a series of
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// copyto/copyfrom virtual register nodes to protect them.
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SmallVector<SDValue, 32> Ops;
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SDValue Chain = TheCall->getChain(), InFlag;
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Ops.push_back(Chain);
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Ops.push_back(TheCall->getCallee());
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for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
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SDValue Arg = TheCall->getArg(i);
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bool isByVal = TheCall->getArgFlags(i).isByVal();
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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if (!isByVal &&
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IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
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MVT VT = Arg.getValueType();
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unsigned VReg = MF.getRegInfo().
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createVirtualRegister(TLI.getRegClassFor(VT));
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Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
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InFlag = Chain.getValue(1);
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Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
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Chain = Arg.getValue(1);
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InFlag = Arg.getValue(2);
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}
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Ops.push_back(Arg);
|
|
Ops.push_back(TheCall->getArgFlagsVal(i));
|
|
}
|
|
// Link in chain of CopyTo/CopyFromReg.
|
|
Ops[0] = Chain;
|
|
DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
|
|
BasicBlock::iterator Begin,
|
|
BasicBlock::iterator End) {
|
|
SDL->setCurrentBasicBlock(BB);
|
|
|
|
// Lower all of the non-terminator instructions.
|
|
for (BasicBlock::iterator I = Begin; I != End; ++I)
|
|
if (!isa<TerminatorInst>(I))
|
|
SDL->visit(*I);
|
|
|
|
// Ensure that all instructions which are used outside of their defining
|
|
// blocks are available as virtual registers. Invoke is handled elsewhere.
|
|
for (BasicBlock::iterator I = Begin; I != End; ++I)
|
|
if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
|
|
DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I);
|
|
if (VMI != FuncInfo->ValueMap.end())
|
|
SDL->CopyValueToVirtualRegister(I, VMI->second);
|
|
}
|
|
|
|
// Handle PHI nodes in successor blocks.
|
|
if (End == LLVMBB->end()) {
|
|
HandlePHINodesInSuccessorBlocks(LLVMBB);
|
|
|
|
// Lower the terminator after the copies are emitted.
|
|
SDL->visit(*LLVMBB->getTerminator());
|
|
}
|
|
|
|
// Make sure the root of the DAG is up-to-date.
|
|
CurDAG->setRoot(SDL->getControlRoot());
|
|
|
|
// Check whether calls in this block are real tail calls. Fix up CALL nodes
|
|
// with correct tailcall attribute so that the target can rely on the tailcall
|
|
// attribute indicating whether the call is really eligible for tail call
|
|
// optimization.
|
|
if (PerformTailCallOpt)
|
|
CheckDAGForTailCallsAndFixThem(*CurDAG, TLI);
|
|
|
|
// Final step, emit the lowered DAG as machine code.
|
|
CodeGenAndEmitDAG();
|
|
SDL->clear();
|
|
}
|
|
|
|
void SelectionDAGISel::ComputeLiveOutVRegInfo() {
|
|
SmallPtrSet<SDNode*, 128> VisitedNodes;
|
|
SmallVector<SDNode*, 128> Worklist;
|
|
|
|
Worklist.push_back(CurDAG->getRoot().getNode());
|
|
|
|
APInt Mask;
|
|
APInt KnownZero;
|
|
APInt KnownOne;
|
|
|
|
while (!Worklist.empty()) {
|
|
SDNode *N = Worklist.back();
|
|
Worklist.pop_back();
|
|
|
|
// If we've already seen this node, ignore it.
|
|
if (!VisitedNodes.insert(N))
|
|
continue;
|
|
|
|
// Otherwise, add all chain operands to the worklist.
|
|
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
|
|
if (N->getOperand(i).getValueType() == MVT::Other)
|
|
Worklist.push_back(N->getOperand(i).getNode());
|
|
|
|
// If this is a CopyToReg with a vreg dest, process it.
|
|
if (N->getOpcode() != ISD::CopyToReg)
|
|
continue;
|
|
|
|
unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
|
|
if (!TargetRegisterInfo::isVirtualRegister(DestReg))
|
|
continue;
|
|
|
|
// Ignore non-scalar or non-integer values.
|
|
SDValue Src = N->getOperand(2);
|
|
MVT SrcVT = Src.getValueType();
|
|
if (!SrcVT.isInteger() || SrcVT.isVector())
|
|
continue;
|
|
|
|
unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
|
|
Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
|
|
CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
|
|
|
|
// Only install this information if it tells us something.
|
|
if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
|
|
DestReg -= TargetRegisterInfo::FirstVirtualRegister;
|
|
FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo();
|
|
if (DestReg >= FLI.LiveOutRegInfo.size())
|
|
FLI.LiveOutRegInfo.resize(DestReg+1);
|
|
FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
|
|
LOI.NumSignBits = NumSignBits;
|
|
LOI.KnownOne = NumSignBits;
|
|
LOI.KnownZero = NumSignBits;
|
|
}
|
|
}
|
|
}
|
|
|
|
void SelectionDAGISel::CodeGenAndEmitDAG() {
|
|
std::string GroupName;
|
|
if (TimePassesIsEnabled)
|
|
GroupName = "Instruction Selection and Scheduling";
|
|
std::string BlockName;
|
|
if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
|
|
ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
|
|
BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' +
|
|
BB->getBasicBlock()->getName();
|
|
|
|
DOUT << "Initial selection DAG:\n";
|
|
DEBUG(CurDAG->dump());
|
|
|
|
if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
|
|
|
|
// Run the DAG combiner in pre-legalize mode.
|
|
if (TimePassesIsEnabled) {
|
|
NamedRegionTimer T("DAG Combining 1", GroupName);
|
|
CurDAG->Combine(false, *AA, Fast);
|
|
} else {
|
|
CurDAG->Combine(false, *AA, Fast);
|
|
}
|
|
|
|
DOUT << "Optimized lowered selection DAG:\n";
|
|
DEBUG(CurDAG->dump());
|
|
|
|
// Second step, hack on the DAG until it only uses operations and types that
|
|
// the target supports.
|
|
if (!DisableLegalizeTypes) {
|
|
if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
|
|
BlockName);
|
|
|
|
if (TimePassesIsEnabled) {
|
|
NamedRegionTimer T("Type Legalization", GroupName);
|
|
CurDAG->LegalizeTypes();
|
|
} else {
|
|
CurDAG->LegalizeTypes();
|
|
}
|
|
|
|
DOUT << "Type-legalized selection DAG:\n";
|
|
DEBUG(CurDAG->dump());
|
|
|
|
// TODO: enable a dag combine pass here.
|
|
}
|
|
|
|
if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
|
|
|
|
if (TimePassesIsEnabled) {
|
|
NamedRegionTimer T("DAG Legalization", GroupName);
|
|
CurDAG->Legalize();
|
|
} else {
|
|
CurDAG->Legalize();
|
|
}
|
|
|
|
DOUT << "Legalized selection DAG:\n";
|
|
DEBUG(CurDAG->dump());
|
|
|
|
if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
|
|
|
|
// Run the DAG combiner in post-legalize mode.
|
|
if (TimePassesIsEnabled) {
|
|
NamedRegionTimer T("DAG Combining 2", GroupName);
|
|
CurDAG->Combine(true, *AA, Fast);
|
|
} else {
|
|
CurDAG->Combine(true, *AA, Fast);
|
|
}
|
|
|
|
DOUT << "Optimized legalized selection DAG:\n";
|
|
DEBUG(CurDAG->dump());
|
|
|
|
if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
|
|
|
|
if (!Fast && EnableValueProp)
|
|
ComputeLiveOutVRegInfo();
|
|
|
|
// Third, instruction select all of the operations to machine code, adding the
|
|
// code to the MachineBasicBlock.
|
|
if (TimePassesIsEnabled) {
|
|
NamedRegionTimer T("Instruction Selection", GroupName);
|
|
InstructionSelect();
|
|
} else {
|
|
InstructionSelect();
|
|
}
|
|
|
|
DOUT << "Selected selection DAG:\n";
|
|
DEBUG(CurDAG->dump());
|
|
|
|
if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
|
|
|
|
// Schedule machine code.
|
|
ScheduleDAG *Scheduler;
|
|
if (TimePassesIsEnabled) {
|
|
NamedRegionTimer T("Instruction Scheduling", GroupName);
|
|
Scheduler = Schedule();
|
|
} else {
|
|
Scheduler = Schedule();
|
|
}
|
|
|
|
if (ViewSUnitDAGs) Scheduler->viewGraph();
|
|
|
|
// Emit machine code to BB. This can change 'BB' to the last block being
|
|
// inserted into.
|
|
if (TimePassesIsEnabled) {
|
|
NamedRegionTimer T("Instruction Creation", GroupName);
|
|
BB = Scheduler->EmitSchedule();
|
|
} else {
|
|
BB = Scheduler->EmitSchedule();
|
|
}
|
|
|
|
// Free the scheduler state.
|
|
if (TimePassesIsEnabled) {
|
|
NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
|
|
delete Scheduler;
|
|
} else {
|
|
delete Scheduler;
|
|
}
|
|
|
|
DOUT << "Selected machine code:\n";
|
|
DEBUG(BB->dump());
|
|
}
|
|
|
|
void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
|
|
MachineModuleInfo *MMI,
|
|
const TargetInstrInfo &TII) {
|
|
// Initialize the Fast-ISel state, if needed.
|
|
FastISel *FastIS = 0;
|
|
if (EnableFastISel)
|
|
FastIS = TLI.createFastISel(*FuncInfo->MF, MMI,
|
|
FuncInfo->ValueMap,
|
|
FuncInfo->MBBMap,
|
|
FuncInfo->StaticAllocaMap
|
|
#ifndef NDEBUG
|
|
, FuncInfo->CatchInfoLost
|
|
#endif
|
|
);
|
|
|
|
// Iterate over all basic blocks in the function.
|
|
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
|
|
BasicBlock *LLVMBB = &*I;
|
|
BB = FuncInfo->MBBMap[LLVMBB];
|
|
|
|
BasicBlock::iterator const Begin = LLVMBB->begin();
|
|
BasicBlock::iterator const End = LLVMBB->end();
|
|
BasicBlock::iterator BI = Begin;
|
|
|
|
// Lower any arguments needed in this block if this is the entry block.
|
|
bool SuppressFastISel = false;
|
|
if (LLVMBB == &Fn.getEntryBlock()) {
|
|
LowerArguments(LLVMBB);
|
|
|
|
// If any of the arguments has the byval attribute, forgo
|
|
// fast-isel in the entry block.
|
|
if (FastIS) {
|
|
unsigned j = 1;
|
|
for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
|
|
I != E; ++I, ++j)
|
|
if (Fn.paramHasAttr(j, Attribute::ByVal)) {
|
|
if (EnableFastISelVerbose || EnableFastISelAbort)
|
|
cerr << "FastISel skips entry block due to byval argument\n";
|
|
SuppressFastISel = true;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (MMI && BB->isLandingPad()) {
|
|
// Add a label to mark the beginning of the landing pad. Deletion of the
|
|
// landing pad can thus be detected via the MachineModuleInfo.
|
|
unsigned LabelID = MMI->addLandingPad(BB);
|
|
|
|
const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL);
|
|
BuildMI(BB, II).addImm(LabelID);
|
|
|
|
// Mark exception register as live in.
|
|
unsigned Reg = TLI.getExceptionAddressRegister();
|
|
if (Reg) BB->addLiveIn(Reg);
|
|
|
|
// Mark exception selector register as live in.
|
|
Reg = TLI.getExceptionSelectorRegister();
|
|
if (Reg) BB->addLiveIn(Reg);
|
|
|
|
// FIXME: Hack around an exception handling flaw (PR1508): the personality
|
|
// function and list of typeids logically belong to the invoke (or, if you
|
|
// like, the basic block containing the invoke), and need to be associated
|
|
// with it in the dwarf exception handling tables. Currently however the
|
|
// information is provided by an intrinsic (eh.selector) that can be moved
|
|
// to unexpected places by the optimizers: if the unwind edge is critical,
|
|
// then breaking it can result in the intrinsics being in the successor of
|
|
// the landing pad, not the landing pad itself. This results in exceptions
|
|
// not being caught because no typeids are associated with the invoke.
|
|
// This may not be the only way things can go wrong, but it is the only way
|
|
// we try to work around for the moment.
|
|
BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
|
|
|
|
if (Br && Br->isUnconditional()) { // Critical edge?
|
|
BasicBlock::iterator I, E;
|
|
for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
|
|
if (isa<EHSelectorInst>(I))
|
|
break;
|
|
|
|
if (I == E)
|
|
// No catch info found - try to extract some from the successor.
|
|
copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
|
|
}
|
|
}
|
|
|
|
// Before doing SelectionDAG ISel, see if FastISel has been requested.
|
|
if (FastIS && !SuppressFastISel) {
|
|
// Emit code for any incoming arguments. This must happen before
|
|
// beginning FastISel on the entry block.
|
|
if (LLVMBB == &Fn.getEntryBlock()) {
|
|
CurDAG->setRoot(SDL->getControlRoot());
|
|
CodeGenAndEmitDAG();
|
|
SDL->clear();
|
|
}
|
|
FastIS->startNewBlock(BB);
|
|
// Do FastISel on as many instructions as possible.
|
|
for (; BI != End; ++BI) {
|
|
// Just before the terminator instruction, insert instructions to
|
|
// feed PHI nodes in successor blocks.
|
|
if (isa<TerminatorInst>(BI))
|
|
if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
|
|
if (EnableFastISelVerbose || EnableFastISelAbort) {
|
|
cerr << "FastISel miss: ";
|
|
BI->dump();
|
|
}
|
|
if (EnableFastISelAbort)
|
|
assert(0 && "FastISel didn't handle a PHI in a successor");
|
|
break;
|
|
}
|
|
|
|
// First try normal tablegen-generated "fast" selection.
|
|
if (FastIS->SelectInstruction(BI))
|
|
continue;
|
|
|
|
// Next, try calling the target to attempt to handle the instruction.
|
|
if (FastIS->TargetSelectInstruction(BI))
|
|
continue;
|
|
|
|
// Then handle certain instructions as single-LLVM-Instruction blocks.
|
|
if (isa<CallInst>(BI)) {
|
|
if (EnableFastISelVerbose || EnableFastISelAbort) {
|
|
cerr << "FastISel missed call: ";
|
|
BI->dump();
|
|
}
|
|
|
|
if (BI->getType() != Type::VoidTy) {
|
|
unsigned &R = FuncInfo->ValueMap[BI];
|
|
if (!R)
|
|
R = FuncInfo->CreateRegForValue(BI);
|
|
}
|
|
|
|
SelectBasicBlock(LLVMBB, BI, next(BI));
|
|
// If the instruction was codegen'd with multiple blocks,
|
|
// inform the FastISel object where to resume inserting.
|
|
FastIS->setCurrentBlock(BB);
|
|
continue;
|
|
}
|
|
|
|
// Otherwise, give up on FastISel for the rest of the block.
|
|
// For now, be a little lenient about non-branch terminators.
|
|
if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
|
|
if (EnableFastISelVerbose || EnableFastISelAbort) {
|
|
cerr << "FastISel miss: ";
|
|
BI->dump();
|
|
}
|
|
if (EnableFastISelAbort)
|
|
// The "fast" selector couldn't handle something and bailed.
|
|
// For the purpose of debugging, just abort.
|
|
assert(0 && "FastISel didn't select the entire block");
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Run SelectionDAG instruction selection on the remainder of the block
|
|
// not handled by FastISel. If FastISel is not run, this is the entire
|
|
// block.
|
|
if (BI != End)
|
|
SelectBasicBlock(LLVMBB, BI, End);
|
|
|
|
FinishBasicBlock();
|
|
}
|
|
|
|
delete FastIS;
|
|
}
|
|
|
|
void
|
|
SelectionDAGISel::FinishBasicBlock() {
|
|
|
|
// Perform target specific isel post processing.
|
|
InstructionSelectPostProcessing();
|
|
|
|
DOUT << "Target-post-processed machine code:\n";
|
|
DEBUG(BB->dump());
|
|
|
|
DOUT << "Total amount of phi nodes to update: "
|
|
<< SDL->PHINodesToUpdate.size() << "\n";
|
|
DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i)
|
|
DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first
|
|
<< ", " << SDL->PHINodesToUpdate[i].second << ")\n";);
|
|
|
|
// Next, now that we know what the last MBB the LLVM BB expanded is, update
|
|
// PHI nodes in successors.
|
|
if (SDL->SwitchCases.empty() &&
|
|
SDL->JTCases.empty() &&
|
|
SDL->BitTestCases.empty()) {
|
|
for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
|
|
MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
"This is not a machine PHI node that we are updating!");
|
|
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
|
|
false));
|
|
PHI->addOperand(MachineOperand::CreateMBB(BB));
|
|
}
|
|
SDL->PHINodesToUpdate.clear();
|
|
return;
|
|
}
|
|
|
|
for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) {
|
|
// Lower header first, if it wasn't already lowered
|
|
if (!SDL->BitTestCases[i].Emitted) {
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
BB = SDL->BitTestCases[i].Parent;
|
|
SDL->setCurrentBasicBlock(BB);
|
|
// Emit the code
|
|
SDL->visitBitTestHeader(SDL->BitTestCases[i]);
|
|
CurDAG->setRoot(SDL->getRoot());
|
|
CodeGenAndEmitDAG();
|
|
SDL->clear();
|
|
}
|
|
|
|
for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
BB = SDL->BitTestCases[i].Cases[j].ThisBB;
|
|
SDL->setCurrentBasicBlock(BB);
|
|
// Emit the code
|
|
if (j+1 != ej)
|
|
SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB,
|
|
SDL->BitTestCases[i].Reg,
|
|
SDL->BitTestCases[i].Cases[j]);
|
|
else
|
|
SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
|
|
SDL->BitTestCases[i].Reg,
|
|
SDL->BitTestCases[i].Cases[j]);
|
|
|
|
|
|
CurDAG->setRoot(SDL->getRoot());
|
|
CodeGenAndEmitDAG();
|
|
SDL->clear();
|
|
}
|
|
|
|
// Update PHI Nodes
|
|
for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
|
|
MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
|
|
MachineBasicBlock *PHIBB = PHI->getParent();
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
"This is not a machine PHI node that we are updating!");
|
|
// This is "default" BB. We have two jumps to it. From "header" BB and
|
|
// from last "case" BB.
|
|
if (PHIBB == SDL->BitTestCases[i].Default) {
|
|
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
|
|
false));
|
|
PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent));
|
|
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
|
|
false));
|
|
PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases.
|
|
back().ThisBB));
|
|
}
|
|
// One of "cases" BB.
|
|
for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size();
|
|
j != ej; ++j) {
|
|
MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB;
|
|
if (cBB->succ_end() !=
|
|
std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
|
|
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
|
|
false));
|
|
PHI->addOperand(MachineOperand::CreateMBB(cBB));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
SDL->BitTestCases.clear();
|
|
|
|
// If the JumpTable record is filled in, then we need to emit a jump table.
|
|
// Updating the PHI nodes is tricky in this case, since we need to determine
|
|
// whether the PHI is a successor of the range check MBB or the jump table MBB
|
|
for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) {
|
|
// Lower header first, if it wasn't already lowered
|
|
if (!SDL->JTCases[i].first.Emitted) {
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
BB = SDL->JTCases[i].first.HeaderBB;
|
|
SDL->setCurrentBasicBlock(BB);
|
|
// Emit the code
|
|
SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first);
|
|
CurDAG->setRoot(SDL->getRoot());
|
|
CodeGenAndEmitDAG();
|
|
SDL->clear();
|
|
}
|
|
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
BB = SDL->JTCases[i].second.MBB;
|
|
SDL->setCurrentBasicBlock(BB);
|
|
// Emit the code
|
|
SDL->visitJumpTable(SDL->JTCases[i].second);
|
|
CurDAG->setRoot(SDL->getRoot());
|
|
CodeGenAndEmitDAG();
|
|
SDL->clear();
|
|
|
|
// Update PHI Nodes
|
|
for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
|
|
MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
|
|
MachineBasicBlock *PHIBB = PHI->getParent();
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
"This is not a machine PHI node that we are updating!");
|
|
// "default" BB. We can go there only from header BB.
|
|
if (PHIBB == SDL->JTCases[i].second.Default) {
|
|
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
|
|
false));
|
|
PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
|
|
}
|
|
// JT BB. Just iterate over successors here
|
|
if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
|
|
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
|
|
false));
|
|
PHI->addOperand(MachineOperand::CreateMBB(BB));
|
|
}
|
|
}
|
|
}
|
|
SDL->JTCases.clear();
|
|
|
|
// If the switch block involved a branch to one of the actual successors, we
|
|
// need to update PHI nodes in that block.
|
|
for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
|
|
MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
"This is not a machine PHI node that we are updating!");
|
|
if (BB->isSuccessor(PHI->getParent())) {
|
|
PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
|
|
false));
|
|
PHI->addOperand(MachineOperand::CreateMBB(BB));
|
|
}
|
|
}
|
|
|
|
// If we generated any switch lowering information, build and codegen any
|
|
// additional DAGs necessary.
|
|
for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
|
|
// Set the current basic block to the mbb we wish to insert the code into
|
|
BB = SDL->SwitchCases[i].ThisBB;
|
|
SDL->setCurrentBasicBlock(BB);
|
|
|
|
// Emit the code
|
|
SDL->visitSwitchCase(SDL->SwitchCases[i]);
|
|
CurDAG->setRoot(SDL->getRoot());
|
|
CodeGenAndEmitDAG();
|
|
SDL->clear();
|
|
|
|
// Handle any PHI nodes in successors of this chunk, as if we were coming
|
|
// from the original BB before switch expansion. Note that PHI nodes can
|
|
// occur multiple times in PHINodesToUpdate. We have to be very careful to
|
|
// handle them the right number of times.
|
|
while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
|
|
for (MachineBasicBlock::iterator Phi = BB->begin();
|
|
Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
|
|
// This value for this PHI node is recorded in PHINodesToUpdate, get it.
|
|
for (unsigned pn = 0; ; ++pn) {
|
|
assert(pn != SDL->PHINodesToUpdate.size() &&
|
|
"Didn't find PHI entry!");
|
|
if (SDL->PHINodesToUpdate[pn].first == Phi) {
|
|
Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
|
|
second, false));
|
|
Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Don't process RHS if same block as LHS.
|
|
if (BB == SDL->SwitchCases[i].FalseBB)
|
|
SDL->SwitchCases[i].FalseBB = 0;
|
|
|
|
// If we haven't handled the RHS, do so now. Otherwise, we're done.
|
|
SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
|
|
SDL->SwitchCases[i].FalseBB = 0;
|
|
}
|
|
assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0);
|
|
}
|
|
SDL->SwitchCases.clear();
|
|
|
|
SDL->PHINodesToUpdate.clear();
|
|
}
|
|
|
|
|
|
/// Schedule - Pick a safe ordering for instructions for each
|
|
/// target node in the graph.
|
|
///
|
|
ScheduleDAG *SelectionDAGISel::Schedule() {
|
|
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
|
|
|
|
if (!Ctor) {
|
|
Ctor = ISHeuristic;
|
|
RegisterScheduler::setDefault(Ctor);
|
|
}
|
|
|
|
TargetMachine &TM = getTargetLowering().getTargetMachine();
|
|
ScheduleDAG *Scheduler = Ctor(this, CurDAG, &TM, BB, Fast);
|
|
Scheduler->Run();
|
|
|
|
return Scheduler;
|
|
}
|
|
|
|
|
|
HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
|
|
return new HazardRecognizer();
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Helper functions used by the generated instruction selector.
|
|
//===----------------------------------------------------------------------===//
|
|
// Calls to these methods are generated by tblgen.
|
|
|
|
/// CheckAndMask - The isel is trying to match something like (and X, 255). If
|
|
/// the dag combiner simplified the 255, we still want to match. RHS is the
|
|
/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
|
|
/// specified in the .td file (e.g. 255).
|
|
bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
|
|
int64_t DesiredMaskS) const {
|
|
const APInt &ActualMask = RHS->getAPIntValue();
|
|
const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
|
|
|
|
// If the actual mask exactly matches, success!
|
|
if (ActualMask == DesiredMask)
|
|
return true;
|
|
|
|
// If the actual AND mask is allowing unallowed bits, this doesn't match.
|
|
if (ActualMask.intersects(~DesiredMask))
|
|
return false;
|
|
|
|
// Otherwise, the DAG Combiner may have proven that the value coming in is
|
|
// either already zero or is not demanded. Check for known zero input bits.
|
|
APInt NeededMask = DesiredMask & ~ActualMask;
|
|
if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
|
|
return true;
|
|
|
|
// TODO: check to see if missing bits are just not demanded.
|
|
|
|
// Otherwise, this pattern doesn't match.
|
|
return false;
|
|
}
|
|
|
|
/// CheckOrMask - The isel is trying to match something like (or X, 255). If
|
|
/// the dag combiner simplified the 255, we still want to match. RHS is the
|
|
/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
|
|
/// specified in the .td file (e.g. 255).
|
|
bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
|
|
int64_t DesiredMaskS) const {
|
|
const APInt &ActualMask = RHS->getAPIntValue();
|
|
const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
|
|
|
|
// If the actual mask exactly matches, success!
|
|
if (ActualMask == DesiredMask)
|
|
return true;
|
|
|
|
// If the actual AND mask is allowing unallowed bits, this doesn't match.
|
|
if (ActualMask.intersects(~DesiredMask))
|
|
return false;
|
|
|
|
// Otherwise, the DAG Combiner may have proven that the value coming in is
|
|
// either already zero or is not demanded. Check for known zero input bits.
|
|
APInt NeededMask = DesiredMask & ~ActualMask;
|
|
|
|
APInt KnownZero, KnownOne;
|
|
CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
|
|
|
|
// If all the missing bits in the or are already known to be set, match!
|
|
if ((NeededMask & KnownOne) == NeededMask)
|
|
return true;
|
|
|
|
// TODO: check to see if missing bits are just not demanded.
|
|
|
|
// Otherwise, this pattern doesn't match.
|
|
return false;
|
|
}
|
|
|
|
|
|
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
|
|
/// by tblgen. Others should not call it.
|
|
void SelectionDAGISel::
|
|
SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
|
|
std::vector<SDValue> InOps;
|
|
std::swap(InOps, Ops);
|
|
|
|
Ops.push_back(InOps[0]); // input chain.
|
|
Ops.push_back(InOps[1]); // input asm string.
|
|
|
|
unsigned i = 2, e = InOps.size();
|
|
if (InOps[e-1].getValueType() == MVT::Flag)
|
|
--e; // Don't process a flag operand if it is here.
|
|
|
|
while (i != e) {
|
|
unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
|
|
if ((Flags & 7) != 4 /*MEM*/) {
|
|
// Just skip over this operand, copying the operands verbatim.
|
|
Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
|
|
i += (Flags >> 3) + 1;
|
|
} else {
|
|
assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
|
|
// Otherwise, this is a memory operand. Ask the target to select it.
|
|
std::vector<SDValue> SelOps;
|
|
if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
|
|
cerr << "Could not match memory address. Inline asm failure!\n";
|
|
exit(1);
|
|
}
|
|
|
|
// Add this to the output node.
|
|
MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
|
|
Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
|
|
IntPtrTy));
|
|
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
|
|
i += 2;
|
|
}
|
|
}
|
|
|
|
// Add the flag input back if present.
|
|
if (e != InOps.size())
|
|
Ops.push_back(InOps.back());
|
|
}
|
|
|
|
char SelectionDAGISel::ID = 0;
|