mirror of
https://github.com/c64scene-ar/llvm-6502.git
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cbfde0a612
* For debugging purposes: + output the predefined bit pattern of the instruction * Fixed inefficiency: only load an operand from MachineInstr once * Bug fix: did not advance bit index when seeing named bit-fields "annul", "cc" and "predict" * Added a catch-all for non-supported instructions at the end of switch stmt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6368 91177308-0d34-0410-b5e6-96231b3b80d8
123 lines
4.2 KiB
C++
123 lines
4.2 KiB
C++
#include "Record.h"
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#include "CodeEmitterGen.h"
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#include <ostream>
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void CodeEmitterGen::createEmitter(std::ostream &o) {
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std::vector<Record*> Insts;
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const std::map<std::string, Record*> &Defs = Records.getDefs();
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Record *Inst = Records.getClass("Instruction");
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assert(Inst && "Couldn't find Instruction class!");
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for (std::map<std::string, Record*>::const_iterator I = Defs.begin(),
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E = Defs.end(); I != E; ++I)
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if (I->second->isSubClassOf(Inst))
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Insts.push_back(I->second);
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std::string Namespace = "V9::";
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std::string ClassName = "SparcV9CodeEmitter::";
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//const std::string &Namespace = Inst->getValue("Namespace")->getName();
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o << "static unsigned " << ClassName
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<< "getBinaryCodeForInstr(MachineInstr &MI) {\n"
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<< " unsigned Value = 0;\n"
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<< " std::cerr << MI;\n"
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<< " switch (MI.getOpcode()) {\n";
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for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
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I != E; ++I)
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{
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Record *R = *I;
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o << " case " << Namespace << R->getName() << ": {\n";
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const RecordVal *InstVal = R->getValue("Inst");
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Init *InitVal = InstVal->getValue();
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assert(dynamic_cast<BitsInit*>(InitVal) &&
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"Can only handle undefined bits<> types!");
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BitsInit *BI = (BitsInit*)InitVal;
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unsigned Value = 0;
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const std::vector<RecordVal> &Vals = R->getValues();
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o << " // prefilling: ";
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// Start by filling in fixed values...
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for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
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if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
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Value |= B->getValue() << (e-i-1);
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o << B->getValue();
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} else {
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o << "0";
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}
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}
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o << "\n\n";
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o << " // " << *InstVal << "\n\n";
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o << " Value = " << Value << "U;\n\n";
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// Loop over all of the fields in the instruction adding in any
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// contributions to this value (due to bit references).
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//
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unsigned op = 0;
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std::map<const std::string,unsigned> OpOrder;
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for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
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if (Vals[i].getName() != "Inst" &&
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!Vals[i].getValue()->isComplete() &&
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Vals[i].getName() != "annul" &&
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Vals[i].getName() != "cc" &&
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Vals[i].getName() != "predict")
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{
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o << " // op" << op << ": " << Vals[i].getName() << "\n"
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<< " int64_t op" << op
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<<" = getMachineOpValue(MI.getOperand("<<op<<"));\n";
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//<< " MachineOperand &op" << op <<" = MI.getOperand("<<op<<");\n";
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OpOrder[Vals[i].getName()] = op++;
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}
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}
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unsigned Offset = 31;
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for (int f = Vals.size()-1; f >= 0; --f) {
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if (Vals[f].getPrefix()) {
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BitsInit *FieldInitializer = (BitsInit*)Vals[f].getValue();
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// Scan through the field looking for bit initializers of the current
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// variable...
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for (int i = FieldInitializer->getNumBits()-1; i >= 0; --i) {
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if (BitInit *BI=dynamic_cast<BitInit*>(FieldInitializer->getBit(i))){
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--Offset;
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} else if (UnsetInit *UI =
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dynamic_cast<UnsetInit*>(FieldInitializer->getBit(i))) {
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--Offset;
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} else if (VarBitInit *VBI =
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dynamic_cast<VarBitInit*>(FieldInitializer->getBit(i))) {
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TypedInit *TI = VBI->getVariable();
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if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
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o << " Value |= getValueBit(op" << OpOrder[VI->getName()]
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<< ", " << VBI->getBitNum()
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<< ")" << " << " << Offset << ";\n";
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--Offset;
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} else if (FieldInit *FI = dynamic_cast<FieldInit*>(TI)) {
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// FIXME: implement this!
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o << "FIELD INIT not implemented yet!\n";
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} else {
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o << "Error: UNIMPLEMENTED\n";
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}
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}
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}
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} else {
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if (Vals[f].getName() == "annul" || Vals[f].getName() == "cc" ||
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Vals[f].getName() == "predict")
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--Offset;
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}
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}
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o << " break;\n"
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<< " }\n";
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}
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o << " default:\n"
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<< " std::cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
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<< " abort();\n"
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<< " }\n"
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<< " return Value;\n"
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<< "}\n";
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}
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