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https://github.com/c64scene-ar/llvm-6502.git
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42faffddb9
DS instructions that access local memory can only uses addresses that are less than or equal to the value of M0. When M0 is uninitialized, then we experience undefined behavior. This patch also changes the behavior to emit S_WQM_B64 on pixel shaders no matter what kind of DS instruction is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201097 91177308-0d34-0410-b5e6-96231b3b80d8
165 lines
6.2 KiB
C++
165 lines
6.2 KiB
C++
//===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for SIInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SIINSTRINFO_H
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#define SIINSTRINFO_H
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#include "AMDGPUInstrInfo.h"
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#include "SIRegisterInfo.h"
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namespace llvm {
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class SIInstrInfo : public AMDGPUInstrInfo {
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private:
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const SIRegisterInfo RI;
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MachineInstrBuilder buildIndirectIndexLoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned OffsetVGPR,
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unsigned MovRelOp,
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unsigned Dst,
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unsigned Src0) const;
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// If you add or remove instructions from this function, you will
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public:
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explicit SIInstrInfo(AMDGPUTargetMachine &tm);
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const SIRegisterInfo &getRegisterInfo() const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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unsigned commuteOpcode(unsigned Opcode) const;
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virtual MachineInstr *commuteInstruction(MachineInstr *MI,
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bool NewMI=false) const;
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virtual unsigned getIEQOpcode() const {
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llvm_unreachable("Unimplemented");
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}
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MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, unsigned SrcReg) const;
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virtual bool isMov(unsigned Opcode) const;
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virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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bool isDS(uint16_t Opcode) const;
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int isMIMG(uint16_t Opcode) const;
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int isSMRD(uint16_t Opcode) const;
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bool isVOP1(uint16_t Opcode) const;
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bool isVOP2(uint16_t Opcode) const;
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bool isVOP3(uint16_t Opcode) const;
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bool isVOPC(uint16_t Opcode) const;
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bool isInlineConstant(const MachineOperand &MO) const;
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bool isLiteralConstant(const MachineOperand &MO) const;
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virtual bool verifyInstruction(const MachineInstr *MI,
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StringRef &ErrInfo) const;
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bool isSALUInstr(const MachineInstr &MI) const;
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static unsigned getVALUOp(const MachineInstr &MI);
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bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
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/// \brief Return the correct register class for \p OpNo. For target-specific
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/// instructions, this will return the register class that has been defined
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/// in tablegen. For generic instructions, like REG_SEQUENCE it will return
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/// the register class of its machine operand.
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/// to infer the correct register class base on the other operands.
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const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
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unsigned OpNo) const;\
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/// \returns true if it is legal for the operand at index \p OpNo
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/// to read a VGPR.
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bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
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/// \brief Legalize the \p OpIndex operand of this instruction by inserting
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/// a MOV. For example:
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/// ADD_I32_e32 VGPR0, 15
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/// to
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/// MOV VGPR1, 15
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/// ADD_I32_e32 VGPR0, VGPR1
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///
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/// If the operand being legalized is a register, then a COPY will be used
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/// instead of MOV.
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void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
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/// \brief Legalize all operands in this instruction. This function may
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/// create new instruction and insert them before \p MI.
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void legalizeOperands(MachineInstr *MI) const;
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/// \brief Replace this instruction's opcode with the equivalent VALU
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/// opcode. This function will also move the users of \p MI to the
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/// VALU if necessary.
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void moveToVALU(MachineInstr &MI) const;
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virtual unsigned calculateIndirectAddress(unsigned RegIndex,
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unsigned Channel) const;
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virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
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virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address,
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unsigned OffsetReg) const;
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virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address,
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unsigned OffsetReg) const;
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void reserveIndirectRegisters(BitVector &Reserved,
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const MachineFunction &MF) const;
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void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
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unsigned SavReg, unsigned IndexReg) const;
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};
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namespace AMDGPU {
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int getVOPe64(uint16_t Opcode);
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int getCommuteRev(uint16_t Opcode);
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int getCommuteOrig(uint16_t Opcode);
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} // End namespace AMDGPU
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} // End namespace llvm
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namespace SIInstrFlags {
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enum Flags {
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// First 4 bits are the instruction encoding
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VM_CNT = 1 << 0,
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EXP_CNT = 1 << 1,
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LGKM_CNT = 1 << 2
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};
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}
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#endif //SIINSTRINFO_H
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