Kit Barton b98636a0f8 While reviewing the changes to Clang to add builtin support for the vsld, vsrd, and vsrad instructions, it was pointed out that the builtins are generating the LLVM opcodes (shl, lshr, and ashr) not calls to the intrinsics. This patch changes the implementation of the vsld, vsrd, and vsrad instructions from from intrinsics to VXForm_1 instructions and makes them legal with P8 Altivec. It also removes the definition of the int_ppc_altivec_vsld, int_ppc_altivec_vsrd, and int_ppc_altivec_vsrad intrinsics. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231378 91177308-0d34-0410-b5e6-96231b3b80d8		2015-03-05 16:24:38 +00:00
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AArch64	Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.	2015-03-04 09:12:08 +00:00
ARM	Improve test robustness	2015-03-04 22:31:18 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips	[mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator	2015-03-04 15:47:42 +00:00
MSP430
NVPTX
PowerPC	While reviewing the changes to Clang to add builtin support for the vsld, vsrd, and vsrad instructions, it was pointed out that the builtins are generating the LLVM opcodes (shl, lshr, and ashr) not calls to the intrinsics. This patch changes the implementation of the vsld, vsrd, and vsrad instructions from from intrinsics to VXForm_1 instructions and makes them legal with P8 Altivec. It also removes the definition of the int_ppc_altivec_vsld, int_ppc_altivec_vsrd, and int_ppc_altivec_vsrad intrinsics.	2015-03-05 16:24:38 +00:00
R600	R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32	2015-03-04 17:33:45 +00:00
SPARC	Use the vanilla func_end symbol for .size.	2015-03-04 01:35:23 +00:00
SystemZ
Thumb
Thumb2	Make DataLayout Non-Optional in the Module	2015-03-04 18:43:29 +00:00
WinEH
X86	Revert change r231366 as it broke clang-native-arm-cortex-a9 Analysis/properties.m test.	2015-03-05 15:41:14 +00:00
XCore