llvm-6502/test/CodeGen
2011-09-02 21:24:17 +00:00
..
Alpha
ARM Revert r131152, r129796, r129761. This code is currently considered 2011-09-01 23:07:08 +00:00
Blackfin
CBackend
CellSPU Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction. 2011-09-02 10:05:01 +00:00
CPP
Generic XFAIL this test on arm until the backend is fixed. 2011-09-01 18:40:03 +00:00
MBlaze
Mips Update for new EH stuff. (I'm not sure if this is 100% correct.) 2011-09-02 21:24:17 +00:00
MSP430
PowerPC Update more tests to the new EH scheme. 2011-08-31 21:04:11 +00:00
PTX
SPARC
SystemZ
Thumb Revert r131152, r129796, r129761. This code is currently considered 2011-09-01 23:07:08 +00:00
Thumb2 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical 2011-08-30 01:34:54 +00:00
X86 Darwin wants ctors/dtors to be ordered the other way round to linux. 2011-09-02 18:07:19 +00:00
XCore Add Uses=[SP] to call instructions. This fixes a miscompilation with a 2011-08-24 13:32:43 +00:00