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https://github.com/c64scene-ar/llvm-6502.git
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6c2be4ff95
For many Thumb-1 register register instructions, setting the CPSR is not permitted inside an IT block. We would not correctly flag those instructions. The previous change to identify this scenario was insufficient as it did not actually catch all the instances. The current list is formed by manual inspection of the ARMv6M ARM. The change to the Thumb2 IT block test is due to the fact that the new more stringent checking of the MIs results in the If Conversion pass being prevented from executing (since not all the instructions in the BB are predicable). This results in code gen changes. Thanks to Tim Northover for pointing out that the previous patch was insufficient and hinting that the use of the v6M ARM would be much easier to use than the v7 or v8! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215382 91177308-0d34-0410-b5e6-96231b3b80d8
31 lines
779 B
LLVM
31 lines
779 B
LLVM
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck -check-prefix CHECK-V7 %s
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; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s -check-prefix CHECK-V8
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; PR11107
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define i32 @test(i32 %a, i32 %b) {
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entry:
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%cmp1 = icmp slt i32 %a, 0
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%sub1 = sub nsw i32 0, %a
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%abs1 = select i1 %cmp1, i32 %sub1, i32 %a
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%cmp2 = icmp slt i32 %b, 0
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%sub2 = sub nsw i32 0, %b
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%abs2 = select i1 %cmp2, i32 %sub2, i32 %b
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%add = add nsw i32 %abs1, %abs2
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ret i32 %add
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}
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; CHECK-V7: cmp
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; CHECK-V7-NEXT: it mi
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; CHECK-V7-NEXT: rsbmi
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; CHECK-V7-NEXT: cmp
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; CHECK-V7-NEXT: it mi
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; CHECK-V7-NEXT: rsbmi
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; CHECK-V8: cmp
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; CHECK-V8-NEXT: bpl
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; CHECK-V8: rsbs
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; CHECK-V8: cmp
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; CHECK-V8-NEXT: bpl
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; CHECK-V8: rsbs
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