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that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
1403 lines
50 KiB
C++
1403 lines
50 KiB
C++
//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMRegisterInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include <algorithm>
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using namespace llvm;
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static cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging",
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cl::Hidden,
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cl::desc("Enable register scavenging on Thumb"));
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unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
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using namespace ARM;
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switch (RegEnum) {
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case R0: case S0: case D0: return 0;
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case R1: case S1: case D1: return 1;
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case R2: case S2: case D2: return 2;
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case R3: case S3: case D3: return 3;
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case R4: case S4: case D4: return 4;
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case R5: case S5: case D5: return 5;
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case R6: case S6: case D6: return 6;
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case R7: case S7: case D7: return 7;
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case R8: case S8: case D8: return 8;
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case R9: case S9: case D9: return 9;
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case R10: case S10: case D10: return 10;
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case R11: case S11: case D11: return 11;
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case R12: case S12: case D12: return 12;
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case SP: case S13: case D13: return 13;
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case LR: case S14: case D14: return 14;
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case PC: case S15: case D15: return 15;
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case S16: return 16;
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case S17: return 17;
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case S18: return 18;
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case S19: return 19;
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case S20: return 20;
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case S21: return 21;
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case S22: return 22;
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case S23: return 23;
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case S24: return 24;
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case S25: return 25;
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case S26: return 26;
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case S27: return 27;
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case S28: return 28;
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case S29: return 29;
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case S30: return 30;
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case S31: return 31;
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default:
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assert(0 && "Unknown ARM register!");
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abort();
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}
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}
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ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
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const ARMSubtarget &sti)
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: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
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TII(tii), STI(sti),
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FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
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}
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static inline
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const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
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return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
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}
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static inline
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const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
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return MIB.addReg(0);
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}
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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static void emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, int Val,
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ARMCC::CondCodes Pred, unsigned PredReg,
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const TargetInstrInfo &TII, bool isThumb) {
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MachineFunction &MF = *MBB.getParent();
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MachineConstantPool *ConstantPool = MF.getConstantPool();
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Constant *C = ConstantInt::get(Type::Int32Ty, Val);
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unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
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if (isThumb)
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BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx);
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else
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BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
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.addReg(0).addImm(0).addImm((unsigned)Pred).addReg(PredReg);
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}
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void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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const MachineInstr *Orig) const {
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if (Orig->getOpcode() == ARM::MOVi2pieces) {
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emitLoadConstPool(MBB, I, DestReg,
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Orig->getOperand(1).getImm(),
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(ARMCC::CondCodes)Orig->getOperand(2).getImm(),
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Orig->getOperand(3).getReg(),
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TII, false);
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return;
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}
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MachineInstr *MI = Orig->clone();
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MI->getOperand(0).setReg(DestReg);
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MBB.insert(I, MI);
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}
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/// isLowRegister - Returns true if the register is low register r0-r7.
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///
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bool ARMRegisterInfo::isLowRegister(unsigned Reg) const {
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using namespace ARM;
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switch (Reg) {
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case R0: case R1: case R2: case R3:
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case R4: case R5: case R6: case R7:
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return true;
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default:
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return false;
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}
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}
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const unsigned*
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ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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static const unsigned CalleeSavedRegs[] = {
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ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
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ARM::R7, ARM::R6, ARM::R5, ARM::R4,
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ARM::D15, ARM::D14, ARM::D13, ARM::D12,
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ARM::D11, ARM::D10, ARM::D9, ARM::D8,
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0
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};
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static const unsigned DarwinCalleeSavedRegs[] = {
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ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
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ARM::R11, ARM::R10, ARM::R9, ARM::R8,
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ARM::D15, ARM::D14, ARM::D13, ARM::D12,
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ARM::D11, ARM::D10, ARM::D9, ARM::D8,
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0
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};
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return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
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}
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const TargetRegisterClass* const *
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ARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
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static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
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&ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
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&ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
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&ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
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&ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
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&ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
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0
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};
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return CalleeSavedRegClasses;
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}
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BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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// FIXME: avoid re-calculating this everytime.
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BitVector Reserved(getNumRegs());
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Reserved.set(ARM::SP);
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Reserved.set(ARM::PC);
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if (STI.isTargetDarwin() || hasFP(MF))
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Reserved.set(FramePtr);
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// Some targets reserve R9.
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if (STI.isR9Reserved())
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Reserved.set(ARM::R9);
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return Reserved;
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}
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bool
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ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
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switch (Reg) {
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default: break;
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case ARM::SP:
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case ARM::PC:
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return true;
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case ARM::R7:
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case ARM::R11:
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if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
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return true;
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break;
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case ARM::R9:
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return STI.isR9Reserved();
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}
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return false;
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}
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bool
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ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
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const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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return ThumbRegScavenging || !AFI->isThumbFunction();
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}
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/// hasFP - Return true if the specified function should have a dedicated frame
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/// pointer register. This is true if the function has variable sized allocas
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/// or if frame pointer elimination is disabled.
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///
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bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
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return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
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}
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// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
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// not required, we reserve argument space for call sites in the function
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// immediately on entry to the current function. This eliminates the need for
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// add/sub sp brackets around call sites. Returns true if the call frame is
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// included as part of the stack frame.
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bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
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const MachineFrameInfo *FFI = MF.getFrameInfo();
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unsigned CFSize = FFI->getMaxCallFrameSize();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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// It's not always a good idea to include the call frame as part of the
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// stack frame. ARM (especially Thumb) has small immediate offset to
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// address the stack frame. So a large call frame can cause poor codegen
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// and may even makes it impossible to scavenge a register.
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if (AFI->isThumbFunction()) {
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if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
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return false;
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} else {
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if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
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return false;
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}
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return !MF.getFrameInfo()->hasVarSizedObjects();
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}
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/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in ARM code.
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static
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void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, unsigned BaseReg, int NumBytes,
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ARMCC::CondCodes Pred, unsigned PredReg,
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const TargetInstrInfo &TII) {
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bool isSub = NumBytes < 0;
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if (isSub) NumBytes = -NumBytes;
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while (NumBytes) {
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unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
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unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
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assert(ThisVal && "Didn't extract field correctly");
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// We will handle these bits from offset, clear them.
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NumBytes &= ~ThisVal;
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// Get the properly encoded SOImmVal field.
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int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
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assert(SOImmVal != -1 && "Bit extraction didn't work?");
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// Build the new ADD / SUB.
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BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
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.addReg(BaseReg, false, false, true).addImm(SOImmVal)
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.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
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BaseReg = DestReg;
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}
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}
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/// calcNumMI - Returns the number of instructions required to materialize
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/// the specific add / sub r, c instruction.
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static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
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unsigned NumBits, unsigned Scale) {
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unsigned NumMIs = 0;
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unsigned Chunk = ((1 << NumBits) - 1) * Scale;
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if (Opc == ARM::tADDrSPi) {
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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Bytes -= ThisVal;
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NumMIs++;
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NumBits = 8;
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Scale = 1; // Followed by a number of tADDi8.
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Chunk = ((1 << NumBits) - 1) * Scale;
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}
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NumMIs += Bytes / Chunk;
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if ((Bytes % Chunk) != 0)
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NumMIs++;
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if (ExtraOpc)
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NumMIs++;
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return NumMIs;
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}
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/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
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/// in a register using mov / mvn sequences or load the immediate from a
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/// constpool entry.
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static
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void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, unsigned BaseReg,
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int NumBytes, bool CanChangeCC,
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const TargetInstrInfo &TII,
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const ARMRegisterInfo& MRI) {
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bool isHigh = !MRI.isLowRegister(DestReg) ||
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(BaseReg != 0 && !MRI.isLowRegister(BaseReg));
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bool isSub = false;
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// Subtract doesn't have high register version. Load the negative value
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// if either base or dest register is a high register. Also, if do not
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// issue sub as part of the sequence if condition register is to be
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// preserved.
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if (NumBytes < 0 && !isHigh && CanChangeCC) {
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isSub = true;
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NumBytes = -NumBytes;
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}
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unsigned LdReg = DestReg;
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if (DestReg == ARM::SP) {
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assert(BaseReg == ARM::SP && "Unexpected!");
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LdReg = ARM::R3;
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BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12)
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.addReg(ARM::R3, false, false, true);
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}
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if (NumBytes <= 255 && NumBytes >= 0)
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BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
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else if (NumBytes < 0 && NumBytes >= -255) {
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BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
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BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
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.addReg(LdReg, false, false, true);
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} else
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emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, TII, true);
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// Emit add / sub.
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int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
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const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
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if (DestReg == ARM::SP || isSub)
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MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
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else
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MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
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if (DestReg == ARM::SP)
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BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3)
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.addReg(ARM::R12, false, false, true);
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}
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/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in Thumb code.
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static
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void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, unsigned BaseReg,
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int NumBytes, const TargetInstrInfo &TII,
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const ARMRegisterInfo& MRI) {
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bool isSub = NumBytes < 0;
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unsigned Bytes = (unsigned)NumBytes;
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if (isSub) Bytes = -NumBytes;
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bool isMul4 = (Bytes & 3) == 0;
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bool isTwoAddr = false;
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bool DstNotEqBase = false;
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unsigned NumBits = 1;
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unsigned Scale = 1;
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int Opc = 0;
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int ExtraOpc = 0;
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if (DestReg == BaseReg && BaseReg == ARM::SP) {
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assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
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NumBits = 7;
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Scale = 4;
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Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
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isTwoAddr = true;
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} else if (!isSub && BaseReg == ARM::SP) {
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// r1 = add sp, 403
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// =>
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// r1 = add sp, 100 * 4
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// r1 = add r1, 3
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if (!isMul4) {
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Bytes &= ~3;
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ExtraOpc = ARM::tADDi3;
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}
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NumBits = 8;
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Scale = 4;
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Opc = ARM::tADDrSPi;
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} else {
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// sp = sub sp, c
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// r1 = sub sp, c
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// r8 = sub sp, c
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if (DestReg != BaseReg)
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DstNotEqBase = true;
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NumBits = 8;
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Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
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isTwoAddr = true;
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}
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unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
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unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
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if (NumMIs > Threshold) {
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// This will expand into too many instructions. Load the immediate from a
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// constpool entry.
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emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII, MRI);
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return;
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}
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if (DstNotEqBase) {
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if (MRI.isLowRegister(DestReg) && MRI.isLowRegister(BaseReg)) {
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// If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
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unsigned Chunk = (1 << 3) - 1;
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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Bytes -= ThisVal;
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BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
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.addReg(BaseReg, false, false, true).addImm(ThisVal);
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} else {
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BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg)
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.addReg(BaseReg, false, false, true);
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}
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BaseReg = DestReg;
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}
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unsigned Chunk = ((1 << NumBits) - 1) * Scale;
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while (Bytes) {
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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Bytes -= ThisVal;
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ThisVal /= Scale;
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// Build the new tADD / tSUB.
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if (isTwoAddr)
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BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
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else {
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bool isKill = BaseReg != ARM::SP;
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BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
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.addReg(BaseReg, false, false, isKill).addImm(ThisVal);
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BaseReg = DestReg;
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|
|
|
if (Opc == ARM::tADDrSPi) {
|
|
// r4 = add sp, imm
|
|
// r4 = add r4, imm
|
|
// ...
|
|
NumBits = 8;
|
|
Scale = 1;
|
|
Chunk = ((1 << NumBits) - 1) * Scale;
|
|
Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
|
|
isTwoAddr = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (ExtraOpc)
|
|
BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
|
|
.addReg(DestReg, false, false, true)
|
|
.addImm(((unsigned)NumBytes) & 3);
|
|
}
|
|
|
|
static
|
|
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
|
int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
|
|
bool isThumb, const TargetInstrInfo &TII,
|
|
const ARMRegisterInfo& MRI) {
|
|
if (isThumb)
|
|
emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, MRI);
|
|
else
|
|
emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
|
|
Pred, PredReg, TII);
|
|
}
|
|
|
|
void ARMRegisterInfo::
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const {
|
|
if (!hasReservedCallFrame(MF)) {
|
|
// If we have alloca, convert as follows:
|
|
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
|
|
// ADJCALLSTACKUP -> add, sp, sp, amount
|
|
MachineInstr *Old = I;
|
|
unsigned Amount = Old->getOperand(0).getImm();
|
|
if (Amount != 0) {
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
// We need to keep the stack aligned properly. To do this, we round the
|
|
// amount of space needed for the outgoing arguments up to the next
|
|
// alignment boundary.
|
|
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
Amount = (Amount+Align-1)/Align*Align;
|
|
|
|
// Replace the pseudo instruction with a new instruction...
|
|
unsigned Opc = Old->getOpcode();
|
|
bool isThumb = AFI->isThumbFunction();
|
|
ARMCC::CondCodes Pred = isThumb
|
|
? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImm();
|
|
if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
|
|
// Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
|
|
unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
|
|
emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this);
|
|
} else {
|
|
// Note: PredReg is operand 3 for ADJCALLSTACKUP.
|
|
unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg();
|
|
assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
|
|
emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this);
|
|
}
|
|
}
|
|
}
|
|
MBB.erase(I);
|
|
}
|
|
|
|
/// emitThumbConstant - Emit a series of instructions to materialize a
|
|
/// constant.
|
|
static void emitThumbConstant(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &MBBI,
|
|
unsigned DestReg, int Imm,
|
|
const TargetInstrInfo &TII,
|
|
const ARMRegisterInfo& MRI) {
|
|
bool isSub = Imm < 0;
|
|
if (isSub) Imm = -Imm;
|
|
|
|
int Chunk = (1 << 8) - 1;
|
|
int ThisVal = (Imm > Chunk) ? Chunk : Imm;
|
|
Imm -= ThisVal;
|
|
BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
|
|
if (Imm > 0)
|
|
emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI);
|
|
if (isSub)
|
|
BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg)
|
|
.addReg(DestReg, false, false, true);
|
|
}
|
|
|
|
/// findScratchRegister - Find a 'free' ARM register. If register scavenger
|
|
/// is not being used, R12 is available. Otherwise, try for a call-clobbered
|
|
/// register first and then a spilled callee-saved register if that fails.
|
|
static
|
|
unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
|
|
ARMFunctionInfo *AFI) {
|
|
unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
|
|
if (Reg == 0)
|
|
// Try a already spilled CS register.
|
|
Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
|
|
|
|
return Reg;
|
|
}
|
|
|
|
void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
int SPAdj, RegScavenger *RS) const{
|
|
unsigned i = 0;
|
|
MachineInstr &MI = *II;
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
MachineFunction &MF = *MBB.getParent();
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
bool isThumb = AFI->isThumbFunction();
|
|
|
|
while (!MI.getOperand(i).isFrameIndex()) {
|
|
++i;
|
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
}
|
|
|
|
unsigned FrameReg = ARM::SP;
|
|
int FrameIndex = MI.getOperand(i).getIndex();
|
|
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
|
|
MF.getFrameInfo()->getStackSize() + SPAdj;
|
|
|
|
if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
|
|
Offset -= AFI->getGPRCalleeSavedArea1Offset();
|
|
else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
|
|
Offset -= AFI->getGPRCalleeSavedArea2Offset();
|
|
else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
|
|
Offset -= AFI->getDPRCalleeSavedAreaOffset();
|
|
else if (hasFP(MF)) {
|
|
assert(SPAdj == 0 && "Unexpected");
|
|
// There is alloca()'s in this function, must reference off the frame
|
|
// pointer instead.
|
|
FrameReg = getFrameRegister(MF);
|
|
Offset -= AFI->getFramePtrSpillOffset();
|
|
}
|
|
|
|
unsigned Opcode = MI.getOpcode();
|
|
const TargetInstrDescriptor &Desc = *MI.getDesc();
|
|
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
|
bool isSub = false;
|
|
|
|
if (Opcode == ARM::ADDri) {
|
|
Offset += MI.getOperand(i+1).getImm();
|
|
if (Offset == 0) {
|
|
// Turn it into a move.
|
|
MI.setInstrDescriptor(TII.get(ARM::MOVr));
|
|
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
|
MI.RemoveOperand(i+1);
|
|
return;
|
|
} else if (Offset < 0) {
|
|
Offset = -Offset;
|
|
isSub = true;
|
|
MI.setInstrDescriptor(TII.get(ARM::SUBri));
|
|
}
|
|
|
|
// Common case: small offset, fits into instruction.
|
|
int ImmedOffset = ARM_AM::getSOImmVal(Offset);
|
|
if (ImmedOffset != -1) {
|
|
// Replace the FrameIndex with sp / fp
|
|
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
|
MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
|
|
return;
|
|
}
|
|
|
|
// Otherwise, we fallback to common code below to form the imm offset with
|
|
// a sequence of ADDri instructions. First though, pull as much of the imm
|
|
// into this ADDri as possible.
|
|
unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
|
|
unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
|
|
|
|
// We will handle these bits from offset, clear them.
|
|
Offset &= ~ThisImmVal;
|
|
|
|
// Get the properly encoded SOImmVal field.
|
|
int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
|
|
assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
|
|
MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
|
|
} else if (Opcode == ARM::tADDrSPi) {
|
|
Offset += MI.getOperand(i+1).getImm();
|
|
|
|
// Can't use tADDrSPi if it's based off the frame pointer.
|
|
unsigned NumBits = 0;
|
|
unsigned Scale = 1;
|
|
if (FrameReg != ARM::SP) {
|
|
Opcode = ARM::tADDi3;
|
|
MI.setInstrDescriptor(TII.get(ARM::tADDi3));
|
|
NumBits = 3;
|
|
} else {
|
|
NumBits = 8;
|
|
Scale = 4;
|
|
assert((Offset & 3) == 0 &&
|
|
"Thumb add/sub sp, #imm immediate must be multiple of 4!");
|
|
}
|
|
|
|
if (Offset == 0) {
|
|
// Turn it into a move.
|
|
MI.setInstrDescriptor(TII.get(ARM::tMOVr));
|
|
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
|
MI.RemoveOperand(i+1);
|
|
return;
|
|
}
|
|
|
|
// Common case: small offset, fits into instruction.
|
|
unsigned Mask = (1 << NumBits) - 1;
|
|
if (((Offset / Scale) & ~Mask) == 0) {
|
|
// Replace the FrameIndex with sp / fp
|
|
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
|
MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
|
|
return;
|
|
}
|
|
|
|
unsigned DestReg = MI.getOperand(0).getReg();
|
|
unsigned Bytes = (Offset > 0) ? Offset : -Offset;
|
|
unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
|
|
// MI would expand into a large number of instructions. Don't try to
|
|
// simplify the immediate.
|
|
if (NumMIs > 2) {
|
|
emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII, *this);
|
|
MBB.erase(II);
|
|
return;
|
|
}
|
|
|
|
if (Offset > 0) {
|
|
// Translate r0 = add sp, imm to
|
|
// r0 = add sp, 255*4
|
|
// r0 = add r0, (imm - 255*4)
|
|
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
|
MI.getOperand(i+1).ChangeToImmediate(Mask);
|
|
Offset = (Offset - Mask * Scale);
|
|
MachineBasicBlock::iterator NII = next(II);
|
|
emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII, *this);
|
|
} else {
|
|
// Translate r0 = add sp, -imm to
|
|
// r0 = -imm (this is then translated into a series of instructons)
|
|
// r0 = add r0, sp
|
|
emitThumbConstant(MBB, II, DestReg, Offset, TII, *this);
|
|
MI.setInstrDescriptor(TII.get(ARM::tADDhirr));
|
|
MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
|
|
MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
|
|
}
|
|
return;
|
|
} else {
|
|
unsigned ImmIdx = 0;
|
|
int InstrOffs = 0;
|
|
unsigned NumBits = 0;
|
|
unsigned Scale = 1;
|
|
switch (AddrMode) {
|
|
case ARMII::AddrMode2: {
|
|
ImmIdx = i+2;
|
|
InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
|
|
if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
|
InstrOffs *= -1;
|
|
NumBits = 12;
|
|
break;
|
|
}
|
|
case ARMII::AddrMode3: {
|
|
ImmIdx = i+2;
|
|
InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
|
|
if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
|
InstrOffs *= -1;
|
|
NumBits = 8;
|
|
break;
|
|
}
|
|
case ARMII::AddrMode5: {
|
|
ImmIdx = i+1;
|
|
InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
|
|
if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
|
InstrOffs *= -1;
|
|
NumBits = 8;
|
|
Scale = 4;
|
|
break;
|
|
}
|
|
case ARMII::AddrModeTs: {
|
|
ImmIdx = i+1;
|
|
InstrOffs = MI.getOperand(ImmIdx).getImm();
|
|
NumBits = (FrameReg == ARM::SP) ? 8 : 5;
|
|
Scale = 4;
|
|
break;
|
|
}
|
|
default:
|
|
assert(0 && "Unsupported addressing mode!");
|
|
abort();
|
|
break;
|
|
}
|
|
|
|
Offset += InstrOffs * Scale;
|
|
assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
|
|
if (Offset < 0 && !isThumb) {
|
|
Offset = -Offset;
|
|
isSub = true;
|
|
}
|
|
|
|
// Common case: small offset, fits into instruction.
|
|
MachineOperand &ImmOp = MI.getOperand(ImmIdx);
|
|
int ImmedOffset = Offset / Scale;
|
|
unsigned Mask = (1 << NumBits) - 1;
|
|
if ((unsigned)Offset <= Mask * Scale) {
|
|
// Replace the FrameIndex with sp
|
|
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
|
if (isSub)
|
|
ImmedOffset |= 1 << NumBits;
|
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
|
return;
|
|
}
|
|
|
|
bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
|
|
if (AddrMode == ARMII::AddrModeTs) {
|
|
// Thumb tLDRspi, tSTRspi. These will change to instructions that use
|
|
// a different base register.
|
|
NumBits = 5;
|
|
Mask = (1 << NumBits) - 1;
|
|
}
|
|
// If this is a thumb spill / restore, we will be using a constpool load to
|
|
// materialize the offset.
|
|
if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
|
|
ImmOp.ChangeToImmediate(0);
|
|
else {
|
|
// Otherwise, it didn't fit. Pull in what we can to simplify the immed.
|
|
ImmedOffset = ImmedOffset & Mask;
|
|
if (isSub)
|
|
ImmedOffset |= 1 << NumBits;
|
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
|
Offset &= ~(Mask*Scale);
|
|
}
|
|
}
|
|
|
|
// If we get here, the immediate doesn't fit into the instruction. We folded
|
|
// as much as possible above, handle the rest, providing a register that is
|
|
// SP+LargeImm.
|
|
assert(Offset && "This code isn't needed if offset already handled!");
|
|
|
|
if (isThumb) {
|
|
if (Desc.isSimpleLoad()) {
|
|
// Use the destination register to materialize sp + offset.
|
|
unsigned TmpReg = MI.getOperand(0).getReg();
|
|
bool UseRR = false;
|
|
if (Opcode == ARM::tRestore) {
|
|
if (FrameReg == ARM::SP)
|
|
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
|
|
Offset, false, TII, *this);
|
|
else {
|
|
emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
|
|
UseRR = true;
|
|
}
|
|
} else
|
|
emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this);
|
|
MI.setInstrDescriptor(TII.get(ARM::tLDR));
|
|
MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
|
|
if (UseRR)
|
|
// Use [reg, reg] addrmode.
|
|
MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
|
|
else // tLDR has an extra register operand.
|
|
MI.addOperand(MachineOperand::CreateReg(0, false));
|
|
} else if (Desc.mayStore()) {
|
|
// FIXME! This is horrific!!! We need register scavenging.
|
|
// Our temporary workaround has marked r3 unavailable. Of course, r3 is
|
|
// also a ABI register so it's possible that is is the register that is
|
|
// being storing here. If that's the case, we do the following:
|
|
// r12 = r2
|
|
// Use r2 to materialize sp + offset
|
|
// str r3, r2
|
|
// r2 = r12
|
|
unsigned ValReg = MI.getOperand(0).getReg();
|
|
unsigned TmpReg = ARM::R3;
|
|
bool UseRR = false;
|
|
if (ValReg == ARM::R3) {
|
|
BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
|
|
.addReg(ARM::R2, false, false, true);
|
|
TmpReg = ARM::R2;
|
|
}
|
|
if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
|
|
BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
|
|
.addReg(ARM::R3, false, false, true);
|
|
if (Opcode == ARM::tSpill) {
|
|
if (FrameReg == ARM::SP)
|
|
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
|
|
Offset, false, TII, *this);
|
|
else {
|
|
emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
|
|
UseRR = true;
|
|
}
|
|
} else
|
|
emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this);
|
|
MI.setInstrDescriptor(TII.get(ARM::tSTR));
|
|
MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
|
|
if (UseRR) // Use [reg, reg] addrmode.
|
|
MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
|
|
else // tSTR has an extra register operand.
|
|
MI.addOperand(MachineOperand::CreateReg(0, false));
|
|
|
|
MachineBasicBlock::iterator NII = next(II);
|
|
if (ValReg == ARM::R3)
|
|
BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2)
|
|
.addReg(ARM::R12, false, false, true);
|
|
if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
|
|
BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3)
|
|
.addReg(ARM::R12, false, false, true);
|
|
} else
|
|
assert(false && "Unexpected opcode!");
|
|
} else {
|
|
// Insert a set of r12 with the full address: r12 = sp + offset
|
|
// If the offset we have is too large to fit into the instruction, we need
|
|
// to form it with a series of ADDri's. Do this by taking 8-bit chunks
|
|
// out of 'Offset'.
|
|
unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
|
|
if (ScratchReg == 0)
|
|
// No register is "free". Scavenge a register.
|
|
ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
|
|
int PIdx = MI.findFirstPredOperandIdx();
|
|
ARMCC::CondCodes Pred = (PIdx == -1)
|
|
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
|
|
unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
|
|
emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
|
|
isSub ? -Offset : Offset, Pred, PredReg, TII);
|
|
MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
|
|
}
|
|
}
|
|
|
|
static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
|
|
const MachineFrameInfo *FFI = MF.getFrameInfo();
|
|
int Offset = 0;
|
|
for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
|
|
int FixedOff = -FFI->getObjectOffset(i);
|
|
if (FixedOff > Offset) Offset = FixedOff;
|
|
}
|
|
for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
|
|
Offset += FFI->getObjectSize(i);
|
|
unsigned Align = FFI->getObjectAlignment(i);
|
|
// Adjust to alignment boundary
|
|
Offset = (Offset+Align-1)/Align*Align;
|
|
}
|
|
return (unsigned)Offset;
|
|
}
|
|
|
|
void
|
|
ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
|
RegScavenger *RS) const {
|
|
// This tells PEI to spill the FP as if it is any other callee-save register
|
|
// to take advantage the eliminateFrameIndex machinery. This also ensures it
|
|
// is spilled in the order specified by getCalleeSavedRegs() to make it easier
|
|
// to combine multiple loads / stores.
|
|
bool CanEliminateFrame = true;
|
|
bool CS1Spilled = false;
|
|
bool LRSpilled = false;
|
|
unsigned NumGPRSpills = 0;
|
|
SmallVector<unsigned, 4> UnspilledCS1GPRs;
|
|
SmallVector<unsigned, 4> UnspilledCS2GPRs;
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
|
|
// Don't spill FP if the frame can be eliminated. This is determined
|
|
// by scanning the callee-save registers to see if any is used.
|
|
const unsigned *CSRegs = getCalleeSavedRegs();
|
|
const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
|
|
for (unsigned i = 0; CSRegs[i]; ++i) {
|
|
unsigned Reg = CSRegs[i];
|
|
bool Spilled = false;
|
|
if (MF.getRegInfo().isPhysRegUsed(Reg)) {
|
|
AFI->setCSRegisterIsSpilled(Reg);
|
|
Spilled = true;
|
|
CanEliminateFrame = false;
|
|
} else {
|
|
// Check alias registers too.
|
|
for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
|
|
if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
|
|
Spilled = true;
|
|
CanEliminateFrame = false;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (CSRegClasses[i] == &ARM::GPRRegClass) {
|
|
if (Spilled) {
|
|
NumGPRSpills++;
|
|
|
|
if (!STI.isTargetDarwin()) {
|
|
if (Reg == ARM::LR)
|
|
LRSpilled = true;
|
|
CS1Spilled = true;
|
|
continue;
|
|
}
|
|
|
|
// Keep track if LR and any of R4, R5, R6, and R7 is spilled.
|
|
switch (Reg) {
|
|
case ARM::LR:
|
|
LRSpilled = true;
|
|
// Fallthrough
|
|
case ARM::R4:
|
|
case ARM::R5:
|
|
case ARM::R6:
|
|
case ARM::R7:
|
|
CS1Spilled = true;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
} else {
|
|
if (!STI.isTargetDarwin()) {
|
|
UnspilledCS1GPRs.push_back(Reg);
|
|
continue;
|
|
}
|
|
|
|
switch (Reg) {
|
|
case ARM::R4:
|
|
case ARM::R5:
|
|
case ARM::R6:
|
|
case ARM::R7:
|
|
case ARM::LR:
|
|
UnspilledCS1GPRs.push_back(Reg);
|
|
break;
|
|
default:
|
|
UnspilledCS2GPRs.push_back(Reg);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
bool ForceLRSpill = false;
|
|
if (!LRSpilled && AFI->isThumbFunction()) {
|
|
unsigned FnSize = ARM::GetFunctionSize(MF);
|
|
// Force LR to be spilled if the Thumb function size is > 2048. This enables
|
|
// use of BL to implement far jump. If it turns out that it's not needed
|
|
// then the branch fix up path will undo it.
|
|
if (FnSize >= (1 << 11)) {
|
|
CanEliminateFrame = false;
|
|
ForceLRSpill = true;
|
|
}
|
|
}
|
|
|
|
bool ExtraCSSpill = false;
|
|
if (!CanEliminateFrame || hasFP(MF)) {
|
|
AFI->setHasStackFrame(true);
|
|
|
|
// If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
|
|
// Spill LR as well so we can fold BX_RET to the registers restore (LDM).
|
|
if (!LRSpilled && CS1Spilled) {
|
|
MF.getRegInfo().setPhysRegUsed(ARM::LR);
|
|
AFI->setCSRegisterIsSpilled(ARM::LR);
|
|
NumGPRSpills++;
|
|
UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
|
|
UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
|
|
ForceLRSpill = false;
|
|
ExtraCSSpill = true;
|
|
}
|
|
|
|
// Darwin ABI requires FP to point to the stack slot that contains the
|
|
// previous FP.
|
|
if (STI.isTargetDarwin() || hasFP(MF)) {
|
|
MF.getRegInfo().setPhysRegUsed(FramePtr);
|
|
NumGPRSpills++;
|
|
}
|
|
|
|
// If stack and double are 8-byte aligned and we are spilling an odd number
|
|
// of GPRs. Spill one extra callee save GPR so we won't have to pad between
|
|
// the integer and double callee save areas.
|
|
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
if (TargetAlign == 8 && (NumGPRSpills & 1)) {
|
|
if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
|
|
for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
|
|
unsigned Reg = UnspilledCS1GPRs[i];
|
|
// Don't spiil high register if the function is thumb
|
|
if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
|
|
MF.getRegInfo().setPhysRegUsed(Reg);
|
|
AFI->setCSRegisterIsSpilled(Reg);
|
|
if (!isReservedReg(MF, Reg))
|
|
ExtraCSSpill = true;
|
|
break;
|
|
}
|
|
}
|
|
} else if (!UnspilledCS2GPRs.empty() &&
|
|
!AFI->isThumbFunction()) {
|
|
unsigned Reg = UnspilledCS2GPRs.front();
|
|
MF.getRegInfo().setPhysRegUsed(Reg);
|
|
AFI->setCSRegisterIsSpilled(Reg);
|
|
if (!isReservedReg(MF, Reg))
|
|
ExtraCSSpill = true;
|
|
}
|
|
}
|
|
|
|
// Estimate if we might need to scavenge a register at some point in order
|
|
// to materialize a stack offset. If so, either spill one additiona
|
|
// callee-saved register or reserve a special spill slot to facilitate
|
|
// register scavenging.
|
|
if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
unsigned Size = estimateStackSize(MF, MFI);
|
|
unsigned Limit = (1 << 12) - 1;
|
|
for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
|
|
for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
|
|
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
|
|
if (I->getOperand(i).isFrameIndex()) {
|
|
unsigned Opcode = I->getOpcode();
|
|
const TargetInstrDescriptor &Desc = TII.get(Opcode);
|
|
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
|
if (AddrMode == ARMII::AddrMode3) {
|
|
Limit = (1 << 8) - 1;
|
|
goto DoneEstimating;
|
|
} else if (AddrMode == ARMII::AddrMode5) {
|
|
unsigned ThisLimit = ((1 << 8) - 1) * 4;
|
|
if (ThisLimit < Limit)
|
|
Limit = ThisLimit;
|
|
}
|
|
}
|
|
}
|
|
DoneEstimating:
|
|
if (Size >= Limit) {
|
|
// If any non-reserved CS register isn't spilled, just spill one or two
|
|
// extra. That should take care of it!
|
|
unsigned NumExtras = TargetAlign / 4;
|
|
SmallVector<unsigned, 2> Extras;
|
|
while (NumExtras && !UnspilledCS1GPRs.empty()) {
|
|
unsigned Reg = UnspilledCS1GPRs.back();
|
|
UnspilledCS1GPRs.pop_back();
|
|
if (!isReservedReg(MF, Reg)) {
|
|
Extras.push_back(Reg);
|
|
NumExtras--;
|
|
}
|
|
}
|
|
while (NumExtras && !UnspilledCS2GPRs.empty()) {
|
|
unsigned Reg = UnspilledCS2GPRs.back();
|
|
UnspilledCS2GPRs.pop_back();
|
|
if (!isReservedReg(MF, Reg)) {
|
|
Extras.push_back(Reg);
|
|
NumExtras--;
|
|
}
|
|
}
|
|
if (Extras.size() && NumExtras == 0) {
|
|
for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
|
|
MF.getRegInfo().setPhysRegUsed(Extras[i]);
|
|
AFI->setCSRegisterIsSpilled(Extras[i]);
|
|
}
|
|
} else {
|
|
// Reserve a slot closest to SP or frame pointer.
|
|
const TargetRegisterClass *RC = &ARM::GPRRegClass;
|
|
RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
|
|
RC->getAlignment()));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (ForceLRSpill) {
|
|
MF.getRegInfo().setPhysRegUsed(ARM::LR);
|
|
AFI->setCSRegisterIsSpilled(ARM::LR);
|
|
AFI->setLRIsSpilledForFarJump(true);
|
|
}
|
|
}
|
|
|
|
/// Move iterator pass the next bunch of callee save load / store ops for
|
|
/// the particular spill area (1: integer area 1, 2: integer area 2,
|
|
/// 3: fp area, 0: don't care).
|
|
static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &MBBI,
|
|
int Opc, unsigned Area,
|
|
const ARMSubtarget &STI) {
|
|
while (MBBI != MBB.end() &&
|
|
MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
|
|
if (Area != 0) {
|
|
bool Done = false;
|
|
unsigned Category = 0;
|
|
switch (MBBI->getOperand(0).getReg()) {
|
|
case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
|
|
case ARM::LR:
|
|
Category = 1;
|
|
break;
|
|
case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
|
|
Category = STI.isTargetDarwin() ? 2 : 1;
|
|
break;
|
|
case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
|
|
case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
|
|
Category = 3;
|
|
break;
|
|
default:
|
|
Done = true;
|
|
break;
|
|
}
|
|
if (Done || Category != Area)
|
|
break;
|
|
}
|
|
|
|
++MBBI;
|
|
}
|
|
}
|
|
|
|
void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
|
MachineBasicBlock &MBB = MF.front();
|
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
bool isThumb = AFI->isThumbFunction();
|
|
unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
|
|
unsigned NumBytes = MFI->getStackSize();
|
|
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
|
|
|
|
if (isThumb) {
|
|
// Check if R3 is live in. It might have to be used as a scratch register.
|
|
for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
|
|
E = MF.getRegInfo().livein_end(); I != E; ++I) {
|
|
if (I->first == ARM::R3) {
|
|
AFI->setR3IsLiveIn(true);
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
|
|
NumBytes = (NumBytes + 3) & ~3;
|
|
MFI->setStackSize(NumBytes);
|
|
}
|
|
|
|
// Determine the sizes of each callee-save spill areas and record which frame
|
|
// belongs to which callee-save spill areas.
|
|
unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
|
|
int FramePtrSpillFI = 0;
|
|
|
|
if (VARegSaveSize)
|
|
emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this);
|
|
|
|
if (!AFI->hasStackFrame()) {
|
|
if (NumBytes != 0)
|
|
emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
|
|
return;
|
|
}
|
|
|
|
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
|
unsigned Reg = CSI[i].getReg();
|
|
int FI = CSI[i].getFrameIdx();
|
|
switch (Reg) {
|
|
case ARM::R4:
|
|
case ARM::R5:
|
|
case ARM::R6:
|
|
case ARM::R7:
|
|
case ARM::LR:
|
|
if (Reg == FramePtr)
|
|
FramePtrSpillFI = FI;
|
|
AFI->addGPRCalleeSavedArea1Frame(FI);
|
|
GPRCS1Size += 4;
|
|
break;
|
|
case ARM::R8:
|
|
case ARM::R9:
|
|
case ARM::R10:
|
|
case ARM::R11:
|
|
if (Reg == FramePtr)
|
|
FramePtrSpillFI = FI;
|
|
if (STI.isTargetDarwin()) {
|
|
AFI->addGPRCalleeSavedArea2Frame(FI);
|
|
GPRCS2Size += 4;
|
|
} else {
|
|
AFI->addGPRCalleeSavedArea1Frame(FI);
|
|
GPRCS1Size += 4;
|
|
}
|
|
break;
|
|
default:
|
|
AFI->addDPRCalleeSavedAreaFrame(FI);
|
|
DPRCSSize += 8;
|
|
}
|
|
}
|
|
|
|
if (!isThumb) {
|
|
// Build the new SUBri to adjust SP for integer callee-save spill area 1.
|
|
emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this);
|
|
movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
|
|
} else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
|
|
++MBBI;
|
|
|
|
// Darwin ABI requires FP to point to the stack slot that contains the
|
|
// previous FP.
|
|
if (STI.isTargetDarwin() || hasFP(MF)) {
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr)
|
|
.addFrameIndex(FramePtrSpillFI).addImm(0);
|
|
if (!isThumb) AddDefaultCC(AddDefaultPred(MIB));
|
|
}
|
|
|
|
if (!isThumb) {
|
|
// Build the new SUBri to adjust SP for integer callee-save spill area 2.
|
|
emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this);
|
|
|
|
// Build the new SUBri to adjust SP for FP callee-save spill area.
|
|
movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
|
|
emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this);
|
|
}
|
|
|
|
// Determine starting offsets of spill areas.
|
|
unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
|
|
unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
|
|
unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
|
|
AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
|
|
AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
|
|
AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
|
|
AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
|
|
|
|
NumBytes = DPRCSOffset;
|
|
if (NumBytes) {
|
|
// Insert it after all the callee-save spills.
|
|
if (!isThumb)
|
|
movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
|
|
emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
|
|
}
|
|
|
|
if(STI.isTargetELF() && hasFP(MF)) {
|
|
MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
|
|
AFI->getFramePtrSpillOffset());
|
|
}
|
|
|
|
AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
|
|
AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
|
|
AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
|
|
}
|
|
|
|
static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
|
|
for (unsigned i = 0; CSRegs[i]; ++i)
|
|
if (Reg == CSRegs[i])
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
|
|
return ((MI->getOpcode() == ARM::FLDD ||
|
|
MI->getOpcode() == ARM::LDR ||
|
|
MI->getOpcode() == ARM::tRestore) &&
|
|
MI->getOperand(1).isFrameIndex() &&
|
|
isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
|
|
}
|
|
|
|
void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const {
|
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
|
assert((MBBI->getOpcode() == ARM::BX_RET ||
|
|
MBBI->getOpcode() == ARM::tBX_RET ||
|
|
MBBI->getOpcode() == ARM::tPOP_RET) &&
|
|
"Can only insert epilog into returning blocks");
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
bool isThumb = AFI->isThumbFunction();
|
|
unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
|
|
int NumBytes = (int)MFI->getStackSize();
|
|
if (!AFI->hasStackFrame()) {
|
|
if (NumBytes != 0)
|
|
emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
|
|
} else {
|
|
// Unwind MBBI to point to first LDR / FLDD.
|
|
const unsigned *CSRegs = getCalleeSavedRegs();
|
|
if (MBBI != MBB.begin()) {
|
|
do
|
|
--MBBI;
|
|
while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
|
|
if (!isCSRestore(MBBI, CSRegs))
|
|
++MBBI;
|
|
}
|
|
|
|
// Move SP to start of FP callee save spill area.
|
|
NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
|
|
AFI->getGPRCalleeSavedArea2Size() +
|
|
AFI->getDPRCalleeSavedAreaSize());
|
|
if (isThumb) {
|
|
if (hasFP(MF)) {
|
|
NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
|
|
// Reset SP based on frame pointer only if the stack frame extends beyond
|
|
// frame pointer stack slot or target is ELF and the function has FP.
|
|
if (NumBytes)
|
|
emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
|
|
TII, *this);
|
|
else
|
|
BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
|
|
} else {
|
|
if (MBBI->getOpcode() == ARM::tBX_RET &&
|
|
&MBB.front() != MBBI &&
|
|
prior(MBBI)->getOpcode() == ARM::tPOP) {
|
|
MachineBasicBlock::iterator PMBBI = prior(MBBI);
|
|
emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
|
|
} else
|
|
emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
|
|
}
|
|
} else {
|
|
// Darwin ABI requires FP to point to the stack slot that contains the
|
|
// previous FP.
|
|
if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
|
|
NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
|
|
// Reset SP based on frame pointer only if the stack frame extends beyond
|
|
// frame pointer stack slot or target is ELF and the function has FP.
|
|
if (AFI->getGPRCalleeSavedArea2Size() ||
|
|
AFI->getDPRCalleeSavedAreaSize() ||
|
|
AFI->getDPRCalleeSavedAreaOffset()||
|
|
hasFP(MF))
|
|
if (NumBytes)
|
|
BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
|
|
.addImm(NumBytes)
|
|
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
|
|
else
|
|
BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
|
|
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
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} else if (NumBytes) {
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emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this);
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}
|
|
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// Move SP to start of integer callee save spill area 2.
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movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
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emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
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false, TII, *this);
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|
|
|
// Move SP to start of integer callee save spill area 1.
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|
movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
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|
emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
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|
false, TII, *this);
|
|
|
|
// Move SP to SP upon entry to the function.
|
|
movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
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|
emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
|
|
false, TII, *this);
|
|
}
|
|
}
|
|
|
|
if (VARegSaveSize) {
|
|
if (isThumb)
|
|
// Epilogue for vararg functions: pop LR to R3 and branch off it.
|
|
// FIXME: Verify this is still ok when R3 is no longer being reserved.
|
|
BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
|
|
|
|
emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this);
|
|
|
|
if (isThumb) {
|
|
BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
|
|
MBB.erase(MBBI);
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned ARMRegisterInfo::getRARegister() const {
|
|
return ARM::LR;
|
|
}
|
|
|
|
unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
|
|
if (STI.isTargetDarwin() || hasFP(MF))
|
|
return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11;
|
|
else
|
|
return ARM::SP;
|
|
}
|
|
|
|
unsigned ARMRegisterInfo::getEHExceptionRegister() const {
|
|
assert(0 && "What is the exception register");
|
|
return 0;
|
|
}
|
|
|
|
unsigned ARMRegisterInfo::getEHHandlerRegister() const {
|
|
assert(0 && "What is the exception handler register");
|
|
return 0;
|
|
}
|
|
|
|
int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
|
|
assert(0 && "What is the dwarf register number");
|
|
return -1;
|
|
}
|
|
|
|
#include "ARMGenRegisterInfo.inc"
|
|
|