Richard Osborne ccb7e96ef0 Expand unaligned 32 bit loads from an address which is a constant ... offset from a 32 bit aligned base as follows: ldw low, base[offset >> 2] ldw high, base[(offset >> 2) + 1] shr low_shifted, low, (offset & 0x3) * 8 shl high_shifted, high, 32 - (offset & 0x3) * 8 or result, low_shifted, high_shifted Expand 32 bit loads / stores with 16 bit alignment into two 16 bit loads / stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75902 91177308-0d34-0410-b5e6-96231b3b80d8		2009-07-16 10:42:35 +00:00
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Alpha	Fix Alpha test and support for private linkage.	2009-01-15 21:51:46 +00:00
ARM	fix an arm codegen bug (the same as PR4482 on ppc) where available_externally	2009-07-15 04:12:33 +00:00
CBackend	Fix an erroneous check for isFNeg; the FNeg case is handled	2009-06-04 23:43:29 +00:00
CellSPU	Add some generic expansion logic for SMULO and UMULO. Fixes UMULO	2009-06-16 06:58:29 +00:00
CPP	Fix code emission for conditional branches.	2009-05-04 19:10:38 +00:00
Generic	remove tests for removed intrinsics.	2009-07-12 21:30:06 +00:00
IA64	Add the private linkage.	2009-01-15 20:18:42 +00:00
Mips	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
MSP430	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
PowerPC	get the PPC stub temporary label from the mangler instead of	2009-07-15 02:56:53 +00:00
SPARC	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
Thumb	Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.	2009-07-11 07:08:13 +00:00
Thumb2	Fix detection of valid BFC immediates.	2009-07-14 00:57:56 +00:00
X86	Let callers decide the sub-register index on the def operand of rematerialized instructions.	2009-07-16 09:20:10 +00:00
XCore	Expand unaligned 32 bit loads from an address which is a constant	2009-07-16 10:42:35 +00:00