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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28752 91177308-0d34-0410-b5e6-96231b3b80d8
809 lines
35 KiB
C++
809 lines
35 KiB
C++
//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes how to lower LLVM code to machine code. This has two
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// main components:
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//
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// 1. Which ValueTypes are natively supported by the target.
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// 2. Which operations are supported for supported ValueTypes.
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// 3. Cost thresholds for alternative implementations of certain operations.
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//
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// In addition it has a few other components, like information about FP
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// immediates.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETLOWERING_H
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#define LLVM_TARGET_TARGETLOWERING_H
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#include "llvm/Type.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include <map>
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namespace llvm {
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class Value;
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class Function;
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class TargetMachine;
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class TargetData;
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class TargetRegisterClass;
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class SDNode;
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class SDOperand;
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class SelectionDAG;
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class MachineBasicBlock;
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class MachineInstr;
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//===----------------------------------------------------------------------===//
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/// TargetLowering - This class defines information used to lower LLVM code to
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/// legal SelectionDAG operators that the target instruction selector can accept
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/// natively.
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///
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/// This class also defines callbacks that targets must implement to lower
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/// target-specific constructs to SelectionDAG operators.
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///
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class TargetLowering {
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public:
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/// LegalizeAction - This enum indicates whether operations are valid for a
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/// target, and if not, what action should be used to make them valid.
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enum LegalizeAction {
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Legal, // The target natively supports this operation.
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Promote, // This operation should be executed in a larger type.
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Expand, // Try to expand this to other ops, otherwise use a libcall.
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Custom // Use the LowerOperation hook to implement custom lowering.
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};
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enum OutOfRangeShiftAmount {
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Undefined, // Oversized shift amounts are undefined (default).
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Mask, // Shift amounts are auto masked (anded) to value size.
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Extend // Oversized shift pulls in zeros or sign bits.
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};
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enum SetCCResultValue {
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UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
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ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
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ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
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};
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enum SchedPreference {
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SchedulingForLatency, // Scheduling for shortest total latency.
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SchedulingForRegPressure // Scheduling for lowest register pressure.
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};
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TargetLowering(TargetMachine &TM);
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virtual ~TargetLowering();
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TargetMachine &getTargetMachine() const { return TM; }
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const TargetData *getTargetData() const { return TD; }
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bool isLittleEndian() const { return IsLittleEndian; }
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MVT::ValueType getPointerTy() const { return PointerTy; }
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MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
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OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
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/// isSetCCExpensive - Return true if the setcc operation is expensive for
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/// this target.
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bool isSetCCExpensive() const { return SetCCIsExpensive; }
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/// isIntDivCheap() - Return true if integer divide is usually cheaper than
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/// a sequence of several shifts, adds, and multiplies for this target.
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bool isIntDivCheap() const { return IntDivIsCheap; }
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/// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
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/// srl/add/sra.
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bool isPow2DivCheap() const { return Pow2DivIsCheap; }
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/// getSetCCResultTy - Return the ValueType of the result of setcc operations.
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///
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MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
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/// getSetCCResultContents - For targets without boolean registers, this flag
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/// returns information about the contents of the high-bits in the setcc
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/// result register.
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SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
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/// getSchedulingPreference - Return target scheduling preference.
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SchedPreference getSchedulingPreference() const {
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return SchedPreferenceInfo;
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}
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/// getRegClassFor - Return the register class that should be used for the
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/// specified value type. This may only be called on legal types.
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TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
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TargetRegisterClass *RC = RegClassForVT[VT];
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assert(RC && "This value type is not natively supported!");
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return RC;
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}
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/// isTypeLegal - Return true if the target has native support for the
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/// specified value type. This means that it has a register that directly
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/// holds it without promotions or expansions.
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bool isTypeLegal(MVT::ValueType VT) const {
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return RegClassForVT[VT] != 0;
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}
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class ValueTypeActionImpl {
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/// ValueTypeActions - This is a bitvector that contains two bits for each
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/// value type, where the two bits correspond to the LegalizeAction enum.
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/// This can be queried with "getTypeAction(VT)".
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uint32_t ValueTypeActions[2];
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public:
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ValueTypeActionImpl() {
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ValueTypeActions[0] = ValueTypeActions[1] = 0;
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}
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ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
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ValueTypeActions[0] = RHS.ValueTypeActions[0];
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ValueTypeActions[1] = RHS.ValueTypeActions[1];
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}
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LegalizeAction getTypeAction(MVT::ValueType VT) const {
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return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
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}
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void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
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assert(unsigned(VT >> 4) <
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sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0]));
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ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
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}
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};
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const ValueTypeActionImpl &getValueTypeActions() const {
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return ValueTypeActions;
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}
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/// getTypeAction - Return how we should legalize values of this type, either
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/// it is already legal (return 'Legal') or we need to promote it to a larger
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/// type (return 'Promote'), or we need to expand it into multiple registers
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/// of smaller integer type (return 'Expand'). 'Custom' is not an option.
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LegalizeAction getTypeAction(MVT::ValueType VT) const {
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return ValueTypeActions.getTypeAction(VT);
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}
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/// getTypeToTransformTo - For types supported by the target, this is an
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/// identity function. For types that must be promoted to larger types, this
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/// returns the larger type to promote to. For types that are larger than the
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/// largest integer register, this contains one step in the expansion to get
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/// to the smaller register.
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MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
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return TransformToType[VT];
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}
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/// getPackedTypeBreakdown - Packed types are broken down into some number of
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/// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32
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/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
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/// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86.
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///
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/// This method returns the number of registers needed, and the VT for each
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/// register. It also returns the VT of the PackedType elements before they
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/// are promoted/expanded.
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///
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unsigned getPackedTypeBreakdown(const PackedType *PTy,
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MVT::ValueType &PTyElementVT,
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MVT::ValueType &PTyLegalElementVT) const;
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typedef std::vector<double>::const_iterator legal_fpimm_iterator;
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legal_fpimm_iterator legal_fpimm_begin() const {
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return LegalFPImmediates.begin();
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}
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legal_fpimm_iterator legal_fpimm_end() const {
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return LegalFPImmediates.end();
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}
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
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/// are assumed to be legal.
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virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
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return true;
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}
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/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
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/// used by Targets can use this to indicate if there is a suitable
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/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
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/// pool entry.
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virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
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MVT::ValueType EVT,
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SelectionDAG &DAG) const {
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return false;
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}
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/// getOperationAction - Return how this operation should be treated: either
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/// it is legal, needs to be promoted to a larger size, needs to be
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/// expanded to some other code sequence, or the target has a custom expander
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/// for it.
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LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
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return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
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}
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/// isOperationLegal - Return true if the specified operation is legal on this
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/// target.
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bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
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return getOperationAction(Op, VT) == Legal ||
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getOperationAction(Op, VT) == Custom;
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}
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/// getTypeToPromoteTo - If the action for this operation is to promote, this
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/// method returns the ValueType to promote to.
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MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
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assert(getOperationAction(Op, VT) == Promote &&
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"This operation isn't promoted!");
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// See if this has an explicit type specified.
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std::map<std::pair<unsigned, MVT::ValueType>,
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MVT::ValueType>::const_iterator PTTI =
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PromoteToType.find(std::make_pair(Op, VT));
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if (PTTI != PromoteToType.end()) return PTTI->second;
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assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
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"Cannot autopromote this type, add it with AddPromotedToType.");
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MVT::ValueType NVT = VT;
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do {
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NVT = (MVT::ValueType)(NVT+1);
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assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
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"Didn't find type to promote to!");
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} while (!isTypeLegal(NVT) ||
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getOperationAction(Op, NVT) == Promote);
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return NVT;
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}
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/// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
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/// This is fixed by the LLVM operations except for the pointer size.
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MVT::ValueType getValueType(const Type *Ty) const {
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switch (Ty->getTypeID()) {
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default: assert(0 && "Unknown type!");
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case Type::VoidTyID: return MVT::isVoid;
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case Type::BoolTyID: return MVT::i1;
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case Type::UByteTyID:
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case Type::SByteTyID: return MVT::i8;
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case Type::ShortTyID:
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case Type::UShortTyID: return MVT::i16;
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case Type::IntTyID:
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case Type::UIntTyID: return MVT::i32;
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case Type::LongTyID:
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case Type::ULongTyID: return MVT::i64;
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case Type::FloatTyID: return MVT::f32;
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case Type::DoubleTyID: return MVT::f64;
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case Type::PointerTyID: return PointerTy;
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case Type::PackedTyID: return MVT::Vector;
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}
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}
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/// getNumElements - Return the number of registers that this ValueType will
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/// eventually require. This is always one for all non-integer types, is
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/// one for any types promoted to live in larger registers, but may be more
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/// than one for types (like i64) that are split into pieces.
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unsigned getNumElements(MVT::ValueType VT) const {
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return NumElementsForVT[VT];
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}
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/// hasTargetDAGCombine - If true, the target has custom DAG combine
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/// transformations that it can perform for the specified node.
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bool hasTargetDAGCombine(ISD::NodeType NT) const {
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return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
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}
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/// This function returns the maximum number of store operations permitted
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/// to replace a call to llvm.memset. The value is set by the target at the
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/// performance threshold for such a replacement.
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/// @brief Get maximum # of store operations permitted for llvm.memset
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unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
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/// This function returns the maximum number of store operations permitted
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/// to replace a call to llvm.memcpy. The value is set by the target at the
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/// performance threshold for such a replacement.
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/// @brief Get maximum # of store operations permitted for llvm.memcpy
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unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
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/// This function returns the maximum number of store operations permitted
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/// to replace a call to llvm.memmove. The value is set by the target at the
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/// performance threshold for such a replacement.
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/// @brief Get maximum # of store operations permitted for llvm.memmove
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unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
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/// This function returns true if the target allows unaligned memory accesses.
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/// This is used, for example, in situations where an array copy/move/set is
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/// converted to a sequence of store operations. It's use helps to ensure that
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/// such replacements don't generate code that causes an alignment error
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/// (trap) on the target machine.
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/// @brief Determine if the target supports unaligned memory accesses.
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bool allowsUnalignedMemoryAccesses() const {
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return allowUnalignedMemoryAccesses;
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}
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/// usesUnderscoreSetJmpLongJmp - Determine if we should use _setjmp or setjmp
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/// to implement llvm.setjmp.
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bool usesUnderscoreSetJmpLongJmp() const {
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return UseUnderscoreSetJmpLongJmp;
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}
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/// getStackPointerRegisterToSaveRestore - If a physical register, this
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/// specifies the register that llvm.savestack/llvm.restorestack should save
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/// and restore.
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unsigned getStackPointerRegisterToSaveRestore() const {
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return StackPointerRegisterToSaveRestore;
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Optimization Methods
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//
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/// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
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/// SDOperands for returning information from TargetLowering to its clients
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/// that want to combine
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struct TargetLoweringOpt {
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SelectionDAG &DAG;
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SDOperand Old;
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SDOperand New;
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TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
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bool CombineTo(SDOperand O, SDOperand N) {
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Old = O;
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New = N;
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return true;
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}
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/// ShrinkDemandedConstant - Check to see if the specified operand of the
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/// specified instruction is a constant integer. If so, check to see if there
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/// are any bits set in the constant that are not demanded. If so, shrink the
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/// constant and return true.
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bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
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};
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/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
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/// use this predicate to simplify operations downstream. Op and Mask are
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/// known to be the same type.
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bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0)
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const;
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/// ComputeMaskedBits - Determine which of the bits specified in Mask are
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/// known to be either zero or one and return them in the KnownZero/KnownOne
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/// bitsets. This code only analyzes bits in Mask, in order to short-circuit
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/// processing. Targets can implement the computeMaskedBitsForTargetNode
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/// method, to allow target nodes to be understood.
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void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero,
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uint64_t &KnownOne, unsigned Depth = 0) const;
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/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
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/// DemandedMask bits of the result of Op are ever used downstream. If we can
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/// use this information to simplify Op, create a new simplified DAG node and
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/// return true, returning the original and new nodes in Old and New.
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/// Otherwise, analyze the expression and return a mask of KnownOne and
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/// KnownZero bits for the expression (used to simplify the caller).
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/// The KnownZero/One bits may only be accurate for those bits in the
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/// DemandedMask.
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bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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uint64_t &KnownZero, uint64_t &KnownOne,
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TargetLoweringOpt &TLO, unsigned Depth = 0) const;
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/// computeMaskedBitsForTargetNode - Determine which of the bits specified in
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/// Mask are known to be either zero or one and return them in the
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/// KnownZero/KnownOne bitsets.
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virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
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uint64_t Mask,
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uint64_t &KnownZero,
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uint64_t &KnownOne,
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unsigned Depth = 0) const;
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/// ComputeNumSignBits - Return the number of times the sign bit of the
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/// register is replicated into the other bits. We know that at least 1 bit
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/// is always equal to the sign bit (itself), but other cases can give us
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/// information. For example, immediately after an "SRA X, 2", we know that
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/// the top 3 bits are all equal to each other, so we return 3.
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unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const;
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/// ComputeNumSignBitsForTargetNode - This method can be implemented by
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/// targets that want to expose additional information about sign bits to the
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/// DAG Combiner.
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virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
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unsigned Depth = 0) const;
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struct DAGCombinerInfo {
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void *DC; // The DAG Combiner object.
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bool BeforeLegalize;
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public:
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SelectionDAG &DAG;
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DAGCombinerInfo(SelectionDAG &dag, bool bl, void *dc)
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: DC(dc), BeforeLegalize(bl), DAG(dag) {}
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bool isBeforeLegalize() const { return BeforeLegalize; }
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void AddToWorklist(SDNode *N);
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SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
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SDOperand CombineTo(SDNode *N, SDOperand Res);
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SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
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};
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/// PerformDAGCombine - This method will be invoked for all target nodes and
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/// for any target-independent nodes that the target has registered with
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/// invoke it for.
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///
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/// The semantics are as follows:
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/// Return Value:
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/// SDOperand.Val == 0 - No change was made
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/// SDOperand.Val == N - N was replaced, is dead, and is already handled.
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/// otherwise - N should be replaced by the returned Operand.
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///
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/// In addition, methods provided by DAGCombinerInfo may be used to perform
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/// more complex transformations.
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///
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virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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//===--------------------------------------------------------------------===//
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// TargetLowering Configuration Methods - These methods should be invoked by
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// the derived class constructor to configure this object for the target.
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//
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protected:
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/// setShiftAmountType - Describe the type that should be used for shift
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/// amounts. This type defaults to the pointer type.
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void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
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/// setSetCCResultType - Describe the type that shoudl be used as the result
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/// of a setcc operation. This defaults to the pointer type.
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void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
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/// setSetCCResultContents - Specify how the target extends the result of a
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/// setcc operation in a register.
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void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
|
|
|
|
/// setSchedulingPreference - Specify the target scheduling preference.
|
|
void setSchedulingPreference(SchedPreference Pref) {
|
|
SchedPreferenceInfo = Pref;
|
|
}
|
|
|
|
/// setShiftAmountFlavor - Describe how the target handles out of range shift
|
|
/// amounts.
|
|
void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
|
|
ShiftAmtHandling = OORSA;
|
|
}
|
|
|
|
/// setUseUnderscoreSetJmpLongJmp - Indicate whether this target prefers to
|
|
/// use _setjmp and _longjmp to or implement llvm.setjmp/llvm.longjmp or
|
|
/// the non _ versions. Defaults to false.
|
|
void setUseUnderscoreSetJmpLongJmp(bool Val) {
|
|
UseUnderscoreSetJmpLongJmp = Val;
|
|
}
|
|
|
|
/// setStackPointerRegisterToSaveRestore - If set to a physical register, this
|
|
/// specifies the register that llvm.savestack/llvm.restorestack should save
|
|
/// and restore.
|
|
void setStackPointerRegisterToSaveRestore(unsigned R) {
|
|
StackPointerRegisterToSaveRestore = R;
|
|
}
|
|
|
|
/// setSetCCIxExpensive - This is a short term hack for targets that codegen
|
|
/// setcc as a conditional branch. This encourages the code generator to fold
|
|
/// setcc operations into other operations if possible.
|
|
void setSetCCIsExpensive() { SetCCIsExpensive = true; }
|
|
|
|
/// setIntDivIsCheap - Tells the code generator that integer divide is
|
|
/// expensive, and if possible, should be replaced by an alternate sequence
|
|
/// of instructions not containing an integer divide.
|
|
void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
|
|
|
|
/// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
|
|
/// srl/add/sra for a signed divide by power of two, and let the target handle
|
|
/// it.
|
|
void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
|
|
|
|
/// addRegisterClass - Add the specified register class as an available
|
|
/// regclass for the specified value type. This indicates the selector can
|
|
/// handle values of that class natively.
|
|
void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
|
|
AvailableRegClasses.push_back(std::make_pair(VT, RC));
|
|
RegClassForVT[VT] = RC;
|
|
}
|
|
|
|
/// computeRegisterProperties - Once all of the register classes are added,
|
|
/// this allows us to compute derived properties we expose.
|
|
void computeRegisterProperties();
|
|
|
|
/// setOperationAction - Indicate that the specified operation does not work
|
|
/// with the specified type and indicate what to do about it.
|
|
void setOperationAction(unsigned Op, MVT::ValueType VT,
|
|
LegalizeAction Action) {
|
|
assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) &&
|
|
"Table isn't big enough!");
|
|
OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
|
|
OpActions[Op] |= (uint64_t)Action << VT*2;
|
|
}
|
|
|
|
/// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
|
|
/// promotion code defaults to trying a larger integer/fp until it can find
|
|
/// one that works. If that default is insufficient, this method can be used
|
|
/// by the target to override the default.
|
|
void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
|
|
MVT::ValueType DestVT) {
|
|
PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
|
|
}
|
|
|
|
/// addLegalFPImmediate - Indicate that this target can instruction select
|
|
/// the specified FP immediate natively.
|
|
void addLegalFPImmediate(double Imm) {
|
|
LegalFPImmediates.push_back(Imm);
|
|
}
|
|
|
|
/// setTargetDAGCombine - Targets should invoke this method for each target
|
|
/// independent node that they want to provide a custom DAG combiner for by
|
|
/// implementing the PerformDAGCombine virtual method.
|
|
void setTargetDAGCombine(ISD::NodeType NT) {
|
|
TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
|
|
}
|
|
|
|
public:
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Lowering methods - These methods must be implemented by targets so that
|
|
// the SelectionDAGLowering code knows how to lower these.
|
|
//
|
|
|
|
/// LowerArguments - This hook must be implemented to indicate how we should
|
|
/// lower the arguments for the specified function, into the specified DAG.
|
|
virtual std::vector<SDOperand>
|
|
LowerArguments(Function &F, SelectionDAG &DAG);
|
|
|
|
/// LowerCallTo - This hook lowers an abstract call to a function into an
|
|
/// actual call. This returns a pair of operands. The first element is the
|
|
/// return value for the function (if RetTy is not VoidTy). The second
|
|
/// element is the outgoing token chain.
|
|
typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy;
|
|
virtual std::pair<SDOperand, SDOperand>
|
|
LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
|
|
unsigned CallingConv, bool isTailCall, SDOperand Callee,
|
|
ArgListTy &Args, SelectionDAG &DAG);
|
|
|
|
/// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or
|
|
/// llvm.frameaddress (depending on the value of the first argument). The
|
|
/// return values are the result pointer and the resultant token chain. If
|
|
/// not implemented, both of these intrinsics will return null.
|
|
virtual std::pair<SDOperand, SDOperand>
|
|
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
|
|
SelectionDAG &DAG);
|
|
|
|
/// LowerOperation - This callback is invoked for operations that are
|
|
/// unsupported by the target, which are registered to use 'custom' lowering,
|
|
/// and whose defined values are all legal.
|
|
/// If the target has no operations that require custom lowering, it need not
|
|
/// implement this. The default implementation of this aborts.
|
|
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
|
|
|
|
/// CustomPromoteOperation - This callback is invoked for operations that are
|
|
/// unsupported by the target, are registered to use 'custom' lowering, and
|
|
/// whose type needs to be promoted.
|
|
virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
|
|
|
|
/// getTargetNodeName() - This method returns the name of a target specific
|
|
/// DAG node.
|
|
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Inline Asm Support hooks
|
|
//
|
|
|
|
enum ConstraintType {
|
|
C_Register, // Constraint represents a single register.
|
|
C_RegisterClass, // Constraint represents one or more registers.
|
|
C_Memory, // Memory constraint.
|
|
C_Other, // Something else.
|
|
C_Unknown // Unsupported constraint.
|
|
};
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
/// constraint it is for this target.
|
|
virtual ConstraintType getConstraintType(char ConstraintLetter) const;
|
|
|
|
|
|
/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
|
|
/// return a list of registers that can be used to satisfy the constraint.
|
|
/// This should only be used for C_RegisterClass constraints.
|
|
virtual std::vector<unsigned>
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
|
MVT::ValueType VT) const;
|
|
|
|
/// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
|
|
/// {edx}), return the register number and the register class for the
|
|
/// register. This should only be used for C_Register constraints. On error,
|
|
/// this returns a register number of 0.
|
|
virtual std::pair<unsigned, const TargetRegisterClass*>
|
|
getRegForInlineAsmConstraint(const std::string &Constraint,
|
|
MVT::ValueType VT) const;
|
|
|
|
|
|
/// isOperandValidForConstraint - Return true if the specified SDOperand is
|
|
/// valid for the specified target constraint letter.
|
|
virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Scheduler hooks
|
|
//
|
|
|
|
// InsertAtEndOfBasicBlock - This method should be implemented by targets that
|
|
// mark instructions with the 'usesCustomDAGSchedInserter' flag. These
|
|
// instructions are special in various ways, which require special support to
|
|
// insert. The specified MachineInstr is created but not inserted into any
|
|
// basic blocks, and the scheduler passes ownership of it to this method.
|
|
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
|
|
MachineBasicBlock *MBB);
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Loop Strength Reduction hooks
|
|
//
|
|
|
|
/// isLegalAddressImmediate - Return true if the integer value or GlobalValue
|
|
/// can be used as the offset of the target addressing mode.
|
|
virtual bool isLegalAddressImmediate(int64_t V) const;
|
|
virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
|
|
|
|
typedef std::vector<unsigned>::const_iterator legal_am_scale_iterator;
|
|
legal_am_scale_iterator legal_am_scale_begin() const {
|
|
return LegalAddressScales.begin();
|
|
}
|
|
legal_am_scale_iterator legal_am_scale_end() const {
|
|
return LegalAddressScales.end();
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Div utility functions
|
|
//
|
|
SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
|
|
std::vector<SDNode*>* Created) const;
|
|
SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
|
|
std::vector<SDNode*>* Created) const;
|
|
|
|
|
|
protected:
|
|
/// addLegalAddressScale - Add a integer (> 1) value which can be used as
|
|
/// scale in the target addressing mode. Note: the ordering matters so the
|
|
/// least efficient ones should be entered first.
|
|
void addLegalAddressScale(unsigned Scale) {
|
|
LegalAddressScales.push_back(Scale);
|
|
}
|
|
|
|
private:
|
|
std::vector<unsigned> LegalAddressScales;
|
|
|
|
TargetMachine &TM;
|
|
const TargetData *TD;
|
|
|
|
/// IsLittleEndian - True if this is a little endian target.
|
|
///
|
|
bool IsLittleEndian;
|
|
|
|
/// PointerTy - The type to use for pointers, usually i32 or i64.
|
|
///
|
|
MVT::ValueType PointerTy;
|
|
|
|
/// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
|
|
/// PointerTy is.
|
|
MVT::ValueType ShiftAmountTy;
|
|
|
|
OutOfRangeShiftAmount ShiftAmtHandling;
|
|
|
|
/// SetCCIsExpensive - This is a short term hack for targets that codegen
|
|
/// setcc as a conditional branch. This encourages the code generator to fold
|
|
/// setcc operations into other operations if possible.
|
|
bool SetCCIsExpensive;
|
|
|
|
/// IntDivIsCheap - Tells the code generator not to expand integer divides by
|
|
/// constants into a sequence of muls, adds, and shifts. This is a hack until
|
|
/// a real cost model is in place. If we ever optimize for size, this will be
|
|
/// set to true unconditionally.
|
|
bool IntDivIsCheap;
|
|
|
|
/// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
|
|
/// srl/add/sra for a signed divide by power of two, and let the target handle
|
|
/// it.
|
|
bool Pow2DivIsCheap;
|
|
|
|
/// SetCCResultTy - The type that SetCC operations use. This defaults to the
|
|
/// PointerTy.
|
|
MVT::ValueType SetCCResultTy;
|
|
|
|
/// SetCCResultContents - Information about the contents of the high-bits in
|
|
/// the result of a setcc comparison operation.
|
|
SetCCResultValue SetCCResultContents;
|
|
|
|
/// SchedPreferenceInfo - The target scheduling preference: shortest possible
|
|
/// total cycles or lowest register usage.
|
|
SchedPreference SchedPreferenceInfo;
|
|
|
|
/// UseUnderscoreSetJmpLongJmp - This target prefers to use _setjmp and
|
|
/// _longjmp to implement llvm.setjmp/llvm.longjmp. Defaults to false.
|
|
bool UseUnderscoreSetJmpLongJmp;
|
|
|
|
/// StackPointerRegisterToSaveRestore - If set to a physical register, this
|
|
/// specifies the register that llvm.savestack/llvm.restorestack should save
|
|
/// and restore.
|
|
unsigned StackPointerRegisterToSaveRestore;
|
|
|
|
/// RegClassForVT - This indicates the default register class to use for
|
|
/// each ValueType the target supports natively.
|
|
TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
|
|
unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
|
|
|
|
/// TransformToType - For any value types we are promoting or expanding, this
|
|
/// contains the value type that we are changing to. For Expanded types, this
|
|
/// contains one step of the expand (e.g. i64 -> i32), even if there are
|
|
/// multiple steps required (e.g. i64 -> i16). For types natively supported
|
|
/// by the system, this holds the same type (e.g. i32 -> i32).
|
|
MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
|
|
|
|
/// OpActions - For each operation and each value type, keep a LegalizeAction
|
|
/// that indicates how instruction selection should deal with the operation.
|
|
/// Most operations are Legal (aka, supported natively by the target), but
|
|
/// operations that are not should be described. Note that operations on
|
|
/// non-legal value types are not described here.
|
|
uint64_t OpActions[156];
|
|
|
|
ValueTypeActionImpl ValueTypeActions;
|
|
|
|
std::vector<double> LegalFPImmediates;
|
|
|
|
std::vector<std::pair<MVT::ValueType,
|
|
TargetRegisterClass*> > AvailableRegClasses;
|
|
|
|
/// TargetDAGCombineArray - Targets can specify ISD nodes that they would
|
|
/// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
|
|
/// which sets a bit in this array.
|
|
unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
|
|
|
|
/// PromoteToType - For operations that must be promoted to a specific type,
|
|
/// this holds the destination type. This map should be sparse, so don't hold
|
|
/// it as an array.
|
|
///
|
|
/// Targets add entries to this map with AddPromotedToType(..), clients access
|
|
/// this with getTypeToPromoteTo(..).
|
|
std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
|
|
|
|
protected:
|
|
/// When lowering %llvm.memset this field specifies the maximum number of
|
|
/// store operations that may be substituted for the call to memset. Targets
|
|
/// must set this value based on the cost threshold for that target. Targets
|
|
/// should assume that the memset will be done using as many of the largest
|
|
/// store operations first, followed by smaller ones, if necessary, per
|
|
/// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
|
|
/// with 16-bit alignment would result in four 2-byte stores and one 1-byte
|
|
/// store. This only applies to setting a constant array of a constant size.
|
|
/// @brief Specify maximum number of store instructions per memset call.
|
|
unsigned maxStoresPerMemset;
|
|
|
|
/// When lowering %llvm.memcpy this field specifies the maximum number of
|
|
/// store operations that may be substituted for a call to memcpy. Targets
|
|
/// must set this value based on the cost threshold for that target. Targets
|
|
/// should assume that the memcpy will be done using as many of the largest
|
|
/// store operations first, followed by smaller ones, if necessary, per
|
|
/// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
|
|
/// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
|
|
/// and one 1-byte store. This only applies to copying a constant array of
|
|
/// constant size.
|
|
/// @brief Specify maximum bytes of store instructions per memcpy call.
|
|
unsigned maxStoresPerMemcpy;
|
|
|
|
/// When lowering %llvm.memmove this field specifies the maximum number of
|
|
/// store instructions that may be substituted for a call to memmove. Targets
|
|
/// must set this value based on the cost threshold for that target. Targets
|
|
/// should assume that the memmove will be done using as many of the largest
|
|
/// store operations first, followed by smaller ones, if necessary, per
|
|
/// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
|
|
/// with 8-bit alignment would result in nine 1-byte stores. This only
|
|
/// applies to copying a constant array of constant size.
|
|
/// @brief Specify maximum bytes of store instructions per memmove call.
|
|
unsigned maxStoresPerMemmove;
|
|
|
|
/// This field specifies whether the target machine permits unaligned memory
|
|
/// accesses. This is used, for example, to determine the size of store
|
|
/// operations when copying small arrays and other similar tasks.
|
|
/// @brief Indicate whether the target permits unaligned memory accesses.
|
|
bool allowUnalignedMemoryAccesses;
|
|
};
|
|
} // end llvm namespace
|
|
|
|
#endif
|