Tom Stellard d3fc10a525 R600/SI: Fix bug where immediates were being used in DS addr operands ... The SelectDS1Addr1Offset complex pattern always tries to store constant lds pointers in the offset operand and store a zero value in the addr operand. Since the addr operand does not accept immediates, the zero value needs to first be copied to a register. This newly created zero value will not go through normal instruction selection, so we need to manually insert a V_MOV_B32_e32 in the complex pattern. This bug was hidden by the fact that if there was another zero value in the DAG that had not been selected yet, then the CSE done by the DAG would use the unselected node for the addr operand rather than the one that was just created. This would lead to the zero value being selected and the DAG automatically inserting a V_MOV_B32_e32 instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219848 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-15 21:08:59 +00:00
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AArch64	Reapply "[FastISel][AArch64] Add custom lowering for GEPs."	2014-10-15 18:58:07 +00:00
ARM	ARM: remove ARM/Thumb distinction for preferred alignment.	2014-10-14 22:12:17 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Mark redundant instructions with a comment in test/CodeGen/Mips/Fast-ISel/icmpa.ll.	2014-10-13 10:18:02 +00:00
MSP430
NVPTX	[MachineSink] Use the real post dominator tree	2014-10-15 03:27:43 +00:00
PowerPC	Improve sqrt estimate algorithm (fast-math)	2014-10-09 21:26:35 +00:00
R600	R600/SI: Fix bug where immediates were being used in DS addr operands	2014-10-15 21:08:59 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	[MachineSink] Use the real post dominator tree	2014-10-15 03:27:43 +00:00
XCore