Juergen Ributzka ccf53013cd [FastISel][AArch64] Fix simplify address when the address comes from a shift. ... When the address comes directly from a shift instruction then the address computation cannot be folded into the memory instruction, because the zero register is not available as a base register. Simplify addess needs to emit the shift instruction and use the result as base register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216621 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-27 21:38:33 +00:00
..
Analysis	InstSimplify: Don't simplify gep X, (Y-X) to Y if types differ	2014-08-27 20:08:34 +00:00
AsmParser
Bitcode	Fix a double free in llvm::getBitcodeTargetTriple.	2014-08-27 21:11:13 +00:00
CodeGen	Group unsafe-math optimizations for fsub into one block. No functional change.	2014-08-27 20:57:52 +00:00
DebugInfo
ExecutionEngine	[MCJIT] Replace a C-style cast in RuntimeDyldImpl.h.	2014-08-27 17:48:07 +00:00
IR	Return a std::unique_ptr when creating a new MemoryBuffer.	2014-08-27 20:03:13 +00:00
IRReader
LineEditor
Linker
LTO	Return a std::unique_ptr when creating a new MemoryBuffer.	2014-08-27 20:03:13 +00:00
MC	Return a std::unique_ptr when creating a new MemoryBuffer.	2014-08-27 20:03:13 +00:00
Object
Option
ProfileData
Support	Return a std::unique_ptr when creating a new MemoryBuffer.	2014-08-27 20:03:13 +00:00
TableGen
Target	[FastISel][AArch64] Fix simplify address when the address comes from a shift.	2014-08-27 21:38:33 +00:00
Transforms	InstCombine: Combine gep X, (Y-X) to Y	2014-08-27 20:08:37 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile