mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5919 91177308-0d34-0410-b5e6-96231b3b80d8
289 lines
11 KiB
C++
289 lines
11 KiB
C++
//===- PromoteMemoryToRegister.cpp - Convert memory refs to regs ----------===//
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//
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// This file is used to promote memory references to be register references. A
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// simple example of the transformation performed by this function is:
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//
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// FROM CODE TO CODE
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// %X = alloca int, uint 1 ret int 42
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// store int 42, int *%X
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// %Y = load int* %X
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// ret int %Y
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//
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// The code is transformed by looping over all of the alloca instruction,
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// calculating dominator frontiers, then inserting phi-nodes following the usual
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// SSA construction algorithm. This code does not modify the CFG of the
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// function.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Transforms/Utils/PromoteMemToReg.h"
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#include "llvm/Analysis/Dominators.h"
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#include "llvm/iMemory.h"
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#include "llvm/iPHINode.h"
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#include "llvm/iTerminators.h"
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#include "llvm/Function.h"
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#include "llvm/Constant.h"
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#include "llvm/Type.h"
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#include "llvm/Support/CFG.h"
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#include "Support/StringExtras.h"
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/// isAllocaPromotable - Return true if this alloca is legal for promotion.
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/// This is true if there are only loads and stores to the alloca...
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///
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bool isAllocaPromotable(const AllocaInst *AI, const TargetData &TD) {
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// FIXME: If the memory unit is of pointer or integer type, we can permit
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// assignments to subsections of the memory unit.
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// Only allow direct loads and stores...
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for (Value::use_const_iterator UI = AI->use_begin(), UE = AI->use_end();
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UI != UE; ++UI) // Loop over all of the uses of the alloca
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if (!isa<LoadInst>(*UI))
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if (const StoreInst *SI = dyn_cast<StoreInst>(*UI)) {
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if (SI->getOperand(0) == AI)
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return false; // Don't allow a store of the AI, only INTO the AI.
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} else {
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return false; // Not a load or store?
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}
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return true;
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}
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namespace {
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struct PromoteMem2Reg {
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const std::vector<AllocaInst*> &Allocas; // the alloca instructions..
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std::vector<unsigned> VersionNumbers; // Current version counters
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DominanceFrontier &DF;
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const TargetData &TD;
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std::map<Instruction*, unsigned> AllocaLookup; // reverse mapping of above
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std::vector<std::vector<BasicBlock*> > PhiNodes;// Idx corresponds 2 Allocas
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// List of instructions to remove at end of pass
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std::vector<Instruction *> KillList;
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std::map<BasicBlock*,
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std::vector<PHINode*> > NewPhiNodes; // the PhiNodes we're adding
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public:
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PromoteMem2Reg(const std::vector<AllocaInst*> &A, DominanceFrontier &df,
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const TargetData &td)
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: Allocas(A), DF(df), TD(td) {}
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void run();
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private:
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void RenamePass(BasicBlock *BB, BasicBlock *Pred,
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std::vector<Value*> &IncVals,
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std::set<BasicBlock*> &Visited);
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bool QueuePhiNode(BasicBlock *BB, unsigned AllocaIdx);
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};
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} // end of anonymous namespace
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void PromoteMem2Reg::run() {
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// If there is nothing to do, bail out...
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if (Allocas.empty()) return;
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Function &F = *DF.getRoot()->getParent();
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VersionNumbers.resize(Allocas.size());
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for (unsigned i = 0, e = Allocas.size(); i != e; ++i) {
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assert(isAllocaPromotable(Allocas[i], TD) &&
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"Cannot promote non-promotable alloca!");
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assert(Allocas[i]->getParent()->getParent() == &F &&
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"All allocas should be in the same function, which is same as DF!");
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AllocaLookup[Allocas[i]] = i;
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}
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// Add each alloca to the KillList. Note: KillList is destroyed MOST recently
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// added to least recently.
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KillList.assign(Allocas.begin(), Allocas.end());
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// Calculate the set of write-locations for each alloca. This is analogous to
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// counting the number of 'redefinitions' of each variable.
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std::vector<std::vector<BasicBlock*> > WriteSets;// Idx corresponds to Allocas
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WriteSets.resize(Allocas.size());
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for (unsigned i = 0; i != Allocas.size(); ++i) {
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AllocaInst *AI = Allocas[i];
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for (Value::use_iterator U =AI->use_begin(), E = AI->use_end(); U != E; ++U)
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if (StoreInst *SI = dyn_cast<StoreInst>(*U))
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// jot down the basic-block it came from
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WriteSets[i].push_back(SI->getParent());
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}
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// Compute the locations where PhiNodes need to be inserted. Look at the
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// dominance frontier of EACH basic-block we have a write in
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//
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PhiNodes.resize(Allocas.size());
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for (unsigned i = 0; i != Allocas.size(); ++i) {
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for (unsigned j = 0; j != WriteSets[i].size(); j++) {
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// Look up the DF for this write, add it to PhiNodes
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DominanceFrontier::const_iterator it = DF.find(WriteSets[i][j]);
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if (it != DF.end()) {
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const DominanceFrontier::DomSetType &S = it->second;
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for (DominanceFrontier::DomSetType::iterator P = S.begin(),PE = S.end();
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P != PE; ++P)
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QueuePhiNode(*P, i);
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}
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}
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// Perform iterative step
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for (unsigned k = 0; k != PhiNodes[i].size(); k++) {
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DominanceFrontier::const_iterator it = DF.find(PhiNodes[i][k]);
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if (it != DF.end()) {
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const DominanceFrontier::DomSetType &S = it->second;
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for (DominanceFrontier::DomSetType::iterator P = S.begin(),PE = S.end();
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P != PE; ++P)
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QueuePhiNode(*P, i);
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}
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}
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}
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// Set the incoming values for the basic block to be null values for all of
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// the alloca's. We do this in case there is a load of a value that has not
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// been stored yet. In this case, it will get this null value.
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//
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std::vector<Value *> Values(Allocas.size());
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for (unsigned i = 0, e = Allocas.size(); i != e; ++i)
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Values[i] = Constant::getNullValue(Allocas[i]->getAllocatedType());
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// Walks all basic blocks in the function performing the SSA rename algorithm
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// and inserting the phi nodes we marked as necessary
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//
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std::set<BasicBlock*> Visited; // The basic blocks we've already visited
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RenamePass(F.begin(), 0, Values, Visited);
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// Remove all instructions marked by being placed in the KillList...
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//
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while (!KillList.empty()) {
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Instruction *I = KillList.back();
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KillList.pop_back();
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// If there are any uses of these instructions left, they must be in
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// sections of dead code that were not processed on the dominance frontier.
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// Just delete the users now.
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//
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while (!I->use_empty()) {
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Instruction *U = cast<Instruction>(I->use_back());
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if (!U->use_empty()) // If uses remain in dead code segment...
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U->replaceAllUsesWith(Constant::getNullValue(U->getType()));
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U->getParent()->getInstList().erase(U);
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}
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I->getParent()->getInstList().erase(I);
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}
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}
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// QueuePhiNode - queues a phi-node to be added to a basic-block for a specific
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// Alloca returns true if there wasn't already a phi-node for that variable
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//
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bool PromoteMem2Reg::QueuePhiNode(BasicBlock *BB, unsigned AllocaNo) {
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// Look up the basic-block in question
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std::vector<PHINode*> &BBPNs = NewPhiNodes[BB];
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if (BBPNs.empty()) BBPNs.resize(Allocas.size());
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// If the BB already has a phi node added for the i'th alloca then we're done!
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if (BBPNs[AllocaNo]) return false;
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// Create a PhiNode using the dereferenced type... and add the phi-node to the
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// BasicBlock.
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PHINode *PN = new PHINode(Allocas[AllocaNo]->getAllocatedType(),
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Allocas[AllocaNo]->getName() + "." +
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utostr(VersionNumbers[AllocaNo]++),
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BB->begin());
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// Add null incoming values for all predecessors. This ensures that if one of
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// the predecessors is not found in the depth-first traversal of the CFG (ie,
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// because it is an unreachable predecessor), that all PHI nodes will have the
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// correct number of entries for their predecessors.
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Value *NullVal = Constant::getNullValue(PN->getType());
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// This is neccesary because adding incoming values to the PHI node adds uses
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// to the basic blocks being used, which can invalidate the predecessor
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// iterator!
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std::vector<BasicBlock*> Preds(pred_begin(BB), pred_end(BB));
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for (unsigned i = 0, e = Preds.size(); i != e; ++i)
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PN->addIncoming(NullVal, Preds[i]);
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BBPNs[AllocaNo] = PN;
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PhiNodes[AllocaNo].push_back(BB);
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return true;
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}
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void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred,
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std::vector<Value*> &IncomingVals,
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std::set<BasicBlock*> &Visited) {
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// If this is a BB needing a phi node, lookup/create the phinode for each
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// variable we need phinodes for.
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std::vector<PHINode *> &BBPNs = NewPhiNodes[BB];
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for (unsigned k = 0; k != BBPNs.size(); ++k)
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if (PHINode *PN = BBPNs[k]) {
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// The PHI node may have multiple entries for this predecessor. We must
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// make sure we update all of them.
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for (unsigned i = 0, e = PN->getNumOperands(); i != e; i += 2) {
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if (PN->getOperand(i+1) == Pred)
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// At this point we can assume that the array has phi nodes.. let's
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// update the incoming data.
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PN->setOperand(i, IncomingVals[k]);
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}
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// also note that the active variable IS designated by the phi node
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IncomingVals[k] = PN;
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}
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// don't revisit nodes
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if (Visited.count(BB)) return;
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// mark as visited
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Visited.insert(BB);
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// keep track of the value of each variable we're watching.. how?
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for (BasicBlock::iterator II = BB->begin(); II != BB->end(); ++II) {
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Instruction *I = II; // get the instruction
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if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
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if (AllocaInst *Src = dyn_cast<AllocaInst>(LI->getPointerOperand())) {
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std::map<Instruction*, unsigned>::iterator AI = AllocaLookup.find(Src);
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if (AI != AllocaLookup.end()) {
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Value *V = IncomingVals[AI->second];
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// walk the use list of this load and replace all uses with r
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LI->replaceAllUsesWith(V);
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KillList.push_back(LI); // Mark the load to be deleted
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}
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}
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} else if (StoreInst *SI = dyn_cast<StoreInst>(I)) {
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// Delete this instruction and mark the name as the current holder of the
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// value
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if (AllocaInst *Dest = dyn_cast<AllocaInst>(SI->getPointerOperand())) {
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std::map<Instruction *, unsigned>::iterator ai =AllocaLookup.find(Dest);
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if (ai != AllocaLookup.end()) {
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// what value were we writing?
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IncomingVals[ai->second] = SI->getOperand(0);
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KillList.push_back(SI); // Mark the store to be deleted
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}
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}
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} else if (TerminatorInst *TI = dyn_cast<TerminatorInst>(I)) {
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// Recurse across our successors
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for (unsigned i = 0; i != TI->getNumSuccessors(); i++) {
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std::vector<Value*> OutgoingVals(IncomingVals);
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RenamePass(TI->getSuccessor(i), BB, OutgoingVals, Visited);
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}
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}
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}
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}
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/// PromoteMemToReg - Promote the specified list of alloca instructions into
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/// scalar registers, inserting PHI nodes as appropriate. This function makes
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/// use of DominanceFrontier information. This function does not modify the CFG
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/// of the function at all. All allocas must be from the same function.
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///
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void PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
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DominanceFrontier &DF, const TargetData &TD) {
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PromoteMem2Reg(Allocas, DF, TD).run();
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}
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