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https://github.com/c64scene-ar/llvm-6502.git
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055b0310f8
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
642 lines
23 KiB
TableGen
642 lines
23 KiB
TableGen
//===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Thumb instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Thumb specific DAG Nodes.
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//
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def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def imm_neg_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
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}]>;
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def imm_comp_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
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}]>;
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/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
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def imm0_7 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 8;
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}]>;
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def imm0_7_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)-N->getZExtValue() < 8;
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}], imm_neg_XFORM>;
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def imm0_255 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 256;
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}]>;
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def imm0_255_comp : PatLeaf<(i32 imm), [{
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return ~((uint32_t)N->getZExtValue()) < 256;
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}]>;
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def imm8_255 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
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}]>;
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def imm8_255_neg : PatLeaf<(i32 imm), [{
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unsigned Val = -N->getZExtValue();
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return Val >= 8 && Val < 256;
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}], imm_neg_XFORM>;
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// Break imm's up into two pieces: an immediate + a left shift.
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// This uses thumb_immshifted to match and thumb_immshifted_val and
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// thumb_immshifted_shamt to get the val/shift pieces.
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def thumb_immshifted : PatLeaf<(imm), [{
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return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
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}]>;
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def thumb_immshifted_val : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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def thumb_immshifted_shamt : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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// Define Thumb specific addressing modes.
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// t_addrmode_rr := reg + reg
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//
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def t_addrmode_rr : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
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let PrintMethod = "printThumbAddrModeRROperand";
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let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
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}
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// t_addrmode_s4 := reg + reg
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// reg + imm5 * 4
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//
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def t_addrmode_s4 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
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let PrintMethod = "printThumbAddrModeS4Operand";
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let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
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}
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// t_addrmode_s2 := reg + reg
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// reg + imm5 * 2
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//
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def t_addrmode_s2 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
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let PrintMethod = "printThumbAddrModeS2Operand";
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let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
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}
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// t_addrmode_s1 := reg + reg
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// reg + imm5
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//
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def t_addrmode_s1 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
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let PrintMethod = "printThumbAddrModeS1Operand";
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let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
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}
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// t_addrmode_sp := sp + imm8 * 4
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//
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def t_addrmode_sp : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
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let PrintMethod = "printThumbAddrModeSPOperand";
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let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
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}
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions.
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//
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let Defs = [SP], Uses = [SP] in {
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def tADJCALLSTACKUP :
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PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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"@ tADJCALLSTACKUP $amt1",
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[(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb]>;
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def tADJCALLSTACKDOWN :
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PseudoInst<(outs), (ins i32imm:$amt),
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"@ tADJCALLSTACKDOWN $amt",
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[(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb]>;
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}
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let isNotDuplicable = 1 in
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def tPICADD : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
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"$cp:\n\tadd $dst, pc",
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[(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
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// PC relative add.
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def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
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"add $dst, pc, $rhs * 4", []>;
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// ADD rd, sp, #imm8
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// FIXME: hard code sp?
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def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
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"add $dst, $sp, $rhs * 4 @ addrspi", []>;
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// ADD sp, sp, #imm7
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// FIXME: hard code sp?
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def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs * 4", []>;
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// FIXME: Make use of the following?
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// ADD rm, sp, rm
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// ADD sp, rm
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions.
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//
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let isReturn = 1, isTerminator = 1 in {
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def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
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// Alternative return instruction used by vararg functions.
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def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), "bx $target", []>;
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}
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// FIXME: remove when we have a way to marking a MI with these properties.
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let isReturn = 1, isTerminator = 1 in
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def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
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"pop $dst1", []>;
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let isCall = 1,
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Defs = [R0, R1, R2, R3, LR,
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D0, D1, D2, D3, D4, D5, D6, D7] in {
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def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops),
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"bl ${func:call}",
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[(ARMtcall tglobaladdr:$func)]>;
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// ARMv5T and above
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def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops),
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"blx ${func:call}",
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[(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
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def tBLXr : TI<(outs), (ins tGPR:$func, variable_ops),
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"blx $func",
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[(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>;
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// ARMv4T
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def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops),
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"cpy lr, pc\n\tbx $func",
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[(ARMcall_nolink tGPR:$func)]>;
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}
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let isBranch = 1, isTerminator = 1 in {
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let isBarrier = 1 in {
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let isPredicable = 1 in
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def tB : TI<(outs), (ins brtarget:$target), "b $target",
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[(br bb:$target)]>;
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// Far jump
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def tBfar : TIx2<(outs), (ins brtarget:$target), "bl $target\t@ far jump",[]>;
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def tBR_JTr : TJTI<(outs),
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(ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
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"cpy pc, $target \n\t.align\t2\n$jt",
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[(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
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}
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}
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// FIXME: should be able to write a pattern for ARMBrcond, but can't use
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// a two-value operand where a dag node expects two operands. :(
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let isBranch = 1, isTerminator = 1 in
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def tBcc : TI<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
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[/*(ARMbrcond bb:$target, imm:$cc)*/]>;
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//===----------------------------------------------------------------------===//
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// Load Store Instructions.
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//
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let canFoldAsLoad = 1 in
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def tLDR : T1I4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr),
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"ldr $dst, $addr",
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[(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
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def tLDRB : T1I1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr),
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"ldrb $dst, $addr",
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[(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
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def tLDRH : T1I2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr),
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"ldrh $dst, $addr",
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[(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
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def tLDRSB : T1I1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
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"ldrsb $dst, $addr",
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[(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
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def tLDRSH : T1I2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
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"ldrsh $dst, $addr",
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[(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
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let canFoldAsLoad = 1 in
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def tLDRspi : T1Is<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
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"ldr $dst, $addr",
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[(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
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// Special instruction for restore. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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let canFoldAsLoad = 1, mayLoad = 1 in
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def tRestore : T1Is<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
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"ldr $dst, $addr", []>;
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// Load tconstpool
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let canFoldAsLoad = 1 in
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def tLDRpci : T1Is<(outs tGPR:$dst), (ins i32imm:$addr),
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"ldr $dst, $addr",
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[(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
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// Special LDR for loads from non-pc-relative constpools.
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let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
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def tLDRcp : T1Is<(outs tGPR:$dst), (ins i32imm:$addr),
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"ldr $dst, $addr", []>;
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def tSTR : T1I4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr),
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"str $src, $addr",
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[(store tGPR:$src, t_addrmode_s4:$addr)]>;
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def tSTRB : T1I1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr),
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"strb $src, $addr",
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[(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
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def tSTRH : T1I2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr),
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"strh $src, $addr",
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[(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
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def tSTRspi : T1Is<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
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"str $src, $addr",
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[(store tGPR:$src, t_addrmode_sp:$addr)]>;
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let mayStore = 1 in {
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// Special instruction for spill. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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def tSpill : T1Is<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
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"str $src, $addr", []>;
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}
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//===----------------------------------------------------------------------===//
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// Load / store multiple Instructions.
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//
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// TODO: A7-44: LDMIA - load multiple
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let mayLoad = 1 in
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def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
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"pop $dst1", []>;
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let mayStore = 1 in
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def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
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"push $src1", []>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions.
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//
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// Add with carry register
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let isCommutable = 1, Defs = [CPSR], Uses = [CPSR] in
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def tADCS : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"adc $dst, $rhs",
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[(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
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// Add immediate
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let Defs = [CPSR] in {
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def tADDi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"add $dst, $lhs, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
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def tADDSi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"add $dst, $lhs, $rhs",
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[(set tGPR:$dst, (addc tGPR:$lhs, imm0_7:$rhs))]>;
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}
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let Defs = [CPSR] in {
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def tADDi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
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def tADDSi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs",
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[(set tGPR:$dst, (addc tGPR:$lhs, imm8_255:$rhs))]>;
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}
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// Add register
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let isCommutable = 1, Defs = [CPSR] in {
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def tADDrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"add $dst, $lhs, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
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def tADDSrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"add $dst, $lhs, $rhs",
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[(set tGPR:$dst, (addc tGPR:$lhs, tGPR:$rhs))]>;
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}
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let neverHasSideEffects = 1 in
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def tADDhirr : T1It<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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"add $dst, $rhs @ addhirr", []>;
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// And register
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let isCommutable = 1, Defs = [CPSR] in
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def tAND : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"and $dst, $rhs",
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[(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
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// ASR immediate
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let Defs = [CPSR] in
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def tASRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"asr $dst, $lhs, $rhs",
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[(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
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// ASR register
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let Defs = [CPSR] in
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def tASRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"asr $dst, $rhs",
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[(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
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// BIC register
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let Defs = [CPSR] in
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def tBIC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"bic $dst, $rhs",
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[(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
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// CMN register
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let Defs = [CPSR] in {
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def tCMN : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmn $lhs, $rhs",
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[(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
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def tCMNNZ : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmn $lhs, $rhs",
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[(ARMcmpNZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
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}
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// CMP immediate
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let Defs = [CPSR] in {
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def tCMPi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
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def tCMPNZi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmpNZ tGPR:$lhs, imm0_255:$rhs)]>;
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}
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// CMP register
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let Defs = [CPSR] in {
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def tCMPr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
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def tCMPNZr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmpNZ tGPR:$lhs, tGPR:$rhs)]>;
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}
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// TODO: A7-37: CMP(3) - cmp hi regs
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// XOR register
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let isCommutable = 1, Defs = [CPSR] in
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def tEOR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"eor $dst, $rhs",
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[(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// LSL immediate
|
|
let Defs = [CPSR] in
|
|
def tLSLri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
|
|
"lsl $dst, $lhs, $rhs",
|
|
[(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
|
|
|
|
// LSL register
|
|
let Defs = [CPSR] in
|
|
def tLSLrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
|
|
"lsl $dst, $rhs",
|
|
[(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// LSR immediate
|
|
let Defs = [CPSR] in
|
|
def tLSRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
|
|
"lsr $dst, $lhs, $rhs",
|
|
[(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
|
|
|
|
// LSR register
|
|
let Defs = [CPSR] in
|
|
def tLSRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
|
|
"lsr $dst, $rhs",
|
|
[(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// move register
|
|
let Defs = [CPSR] in
|
|
def tMOVi8 : T1I<(outs tGPR:$dst), (ins i32imm:$src),
|
|
"mov $dst, $src",
|
|
[(set tGPR:$dst, imm0_255:$src)]>;
|
|
|
|
// TODO: A7-73: MOV(2) - mov setting flag.
|
|
|
|
|
|
// Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
|
|
// which is MOV(3). This also supports high registers.
|
|
let neverHasSideEffects = 1 in {
|
|
def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
|
|
"cpy $dst, $src", []>;
|
|
def tMOVhir2lor : T1I<(outs tGPR:$dst), (ins GPR:$src),
|
|
"cpy $dst, $src\t@ hir2lor", []>;
|
|
def tMOVlor2hir : T1I<(outs GPR:$dst), (ins tGPR:$src),
|
|
"cpy $dst, $src\t@ lor2hir", []>;
|
|
def tMOVhir2hir : T1I<(outs GPR:$dst), (ins GPR:$src),
|
|
"cpy $dst, $src\t@ hir2hir", []>;
|
|
} // neverHasSideEffects
|
|
|
|
// multiply register
|
|
let isCommutable = 1, Defs = [CPSR] in
|
|
def tMUL : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
|
|
"mul $dst, $rhs",
|
|
[(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// move inverse register
|
|
let Defs = [CPSR] in
|
|
def tMVN : T1I<(outs tGPR:$dst), (ins tGPR:$src),
|
|
"mvn $dst, $src",
|
|
[(set tGPR:$dst, (not tGPR:$src))]>;
|
|
|
|
// negate register
|
|
let Defs = [CPSR] in
|
|
def tNEG : T1I<(outs tGPR:$dst), (ins tGPR:$src),
|
|
"neg $dst, $src",
|
|
[(set tGPR:$dst, (ineg tGPR:$src))]>;
|
|
|
|
// bitwise or register
|
|
let isCommutable = 1, Defs = [CPSR] in
|
|
def tORR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
|
|
"orr $dst, $rhs",
|
|
[(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// swaps
|
|
def tREV : T1I<(outs tGPR:$dst), (ins tGPR:$src),
|
|
"rev $dst, $src",
|
|
[(set tGPR:$dst, (bswap tGPR:$src))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
def tREV16 : T1I<(outs tGPR:$dst), (ins tGPR:$src),
|
|
"rev16 $dst, $src",
|
|
[(set tGPR:$dst,
|
|
(or (and (srl tGPR:$src, (i32 8)), 0xFF),
|
|
(or (and (shl tGPR:$src, (i32 8)), 0xFF00),
|
|
(or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
|
|
(and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
def tREVSH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
|
|
"revsh $dst, $src",
|
|
[(set tGPR:$dst,
|
|
(sext_inreg
|
|
(or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
|
|
(shl tGPR:$src, (i32 8))), i16))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
// rotate right register
|
|
let Defs = [CPSR] in
|
|
def tROR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
|
|
"ror $dst, $rhs",
|
|
[(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// Subtract with carry register
|
|
let Defs = [CPSR], Uses = [CPSR] in
|
|
def tSBCS : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
|
|
"sbc $dst, $rhs",
|
|
[(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// Subtract immediate
|
|
let Defs = [CPSR] in {
|
|
def tSUBi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
|
|
"sub $dst, $lhs, $rhs",
|
|
[(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
|
|
def tSUBSi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
|
|
"sub $dst, $lhs, $rhs",
|
|
[(set tGPR:$dst, (addc tGPR:$lhs, imm0_7_neg:$rhs))]>;
|
|
}
|
|
|
|
let Defs = [CPSR] in {
|
|
def tSUBi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
|
|
"sub $dst, $rhs",
|
|
[(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
|
|
def tSUBSi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
|
|
"sub $dst, $rhs",
|
|
[(set tGPR:$dst, (addc tGPR:$lhs, imm8_255_neg:$rhs))]>;
|
|
}
|
|
|
|
// subtract register
|
|
let Defs = [CPSR] in {
|
|
def tSUBrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
|
|
"sub $dst, $lhs, $rhs",
|
|
[(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
|
|
def tSUBSrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
|
|
"sub $dst, $lhs, $rhs",
|
|
[(set tGPR:$dst, (subc tGPR:$lhs, tGPR:$rhs))]>;
|
|
}
|
|
|
|
// TODO: A7-96: STMIA - store multiple.
|
|
|
|
def tSUBspi : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
|
|
"sub $dst, $rhs * 4", []>;
|
|
|
|
// sign-extend byte
|
|
def tSXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
|
|
"sxtb $dst, $src",
|
|
[(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
// sign-extend short
|
|
def tSXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
|
|
"sxth $dst, $src",
|
|
[(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
// test
|
|
let isCommutable = 1, Defs = [CPSR] in
|
|
def tTST : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
|
|
"tst $lhs, $rhs",
|
|
[(ARMcmpNZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
|
|
|
|
// zero-extend byte
|
|
def tUXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
|
|
"uxtb $dst, $src",
|
|
[(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
// zero-extend short
|
|
def tUXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
|
|
"uxth $dst, $src",
|
|
[(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
|
|
// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
|
|
// Expanded by the scheduler into a branch sequence.
|
|
let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
|
|
def tMOVCCr :
|
|
PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
|
|
"@ tMOVCCr $cc",
|
|
[/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
|
|
|
|
// tLEApcrel - Load a pc-relative address into a register without offending the
|
|
// assembler.
|
|
def tLEApcrel : TIx2<(outs tGPR:$dst), (ins i32imm:$label),
|
|
!strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
|
|
"${:private}PCRELL${:uid}+4))\n"),
|
|
!strconcat("\tmov $dst, #PCRELV${:uid}\n",
|
|
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
|
|
[]>;
|
|
|
|
def tLEApcrelJT : TIx2<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
|
|
!strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
|
|
"${:private}PCRELL${:uid}+4))\n"),
|
|
!strconcat("\tmov $dst, #PCRELV${:uid}\n",
|
|
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
|
|
[]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// TLS Instructions
|
|
//
|
|
|
|
// __aeabi_read_tp preserves the registers r1-r3.
|
|
let isCall = 1,
|
|
Defs = [R0, LR] in {
|
|
def tTPsoft : TIx2<(outs), (ins),
|
|
"bl __aeabi_read_tp",
|
|
[(set R0, ARMthread_pointer)]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
//
|
|
|
|
// ConstantPool, GlobalAddress
|
|
def : TPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
|
|
def : TPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
|
|
|
|
// JumpTable
|
|
def : TPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
|
|
(tLEApcrelJT tjumptable:$dst, imm:$id)>;
|
|
|
|
// Direct calls
|
|
def : TPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
|
|
def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
|
|
|
|
// Indirect calls to ARM routines
|
|
def : Tv5Pat<(ARMcall tGPR:$dst), (tBLXr tGPR:$dst)>;
|
|
|
|
// zextload i1 -> zextload i8
|
|
def : TPat<(zextloadi1 t_addrmode_s1:$addr),
|
|
(tLDRB t_addrmode_s1:$addr)>;
|
|
|
|
// extload -> zextload
|
|
def : TPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
|
|
def : TPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
|
|
def : TPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
|
|
|
|
// Large immediate handling.
|
|
|
|
// Two piece imms.
|
|
def : T1Pat<(i32 thumb_immshifted:$src),
|
|
(tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
|
|
(thumb_immshifted_shamt imm:$src))>;
|
|
|
|
def : T1Pat<(i32 imm0_255_comp:$src),
|
|
(tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
|