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In case the MachineScheduling pass I'm working on doesn't work well for another target, they can completely override it. This also adds a hook immediately after the RegAlloc pass to cleanup immediately after vregs go away. We may want to fold it into the postRA hook later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150298 91177308-0d34-0410-b5e6-96231b3b80d8
535 lines
20 KiB
C++
535 lines
20 KiB
C++
//===-- Passes.cpp - Target independent code generation passes ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines interfaces to access the target independent code
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// generation passes provided by the LLVM backend.
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//
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//===---------------------------------------------------------------------===//
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#include "llvm/Analysis/Passes.h"
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#include "llvm/Analysis/Verifier.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/GCStrategy.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
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cl::desc("Disable Post Regalloc"));
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static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
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cl::desc("Disable branch folding"));
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static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
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cl::desc("Disable tail duplication"));
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static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
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cl::desc("Disable pre-register allocation tail duplication"));
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static cl::opt<bool> EnableBlockPlacement("enable-block-placement",
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cl::Hidden, cl::desc("Enable probability-driven block placement"));
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static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
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cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
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static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
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cl::desc("Disable code placement"));
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static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
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cl::desc("Disable Stack Slot Coloring"));
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static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
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cl::desc("Disable Machine Dead Code Elimination"));
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static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
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cl::desc("Disable Machine LICM"));
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static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
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cl::desc("Disable Machine Common Subexpression Elimination"));
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static cl::opt<cl::boolOrDefault>
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OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
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cl::desc("Enable optimized register allocation compilation path."));
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static cl::opt<cl::boolOrDefault>
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EnableMachineSched("enable-misched", cl::Hidden,
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cl::desc("Enable the machine instruction scheduling pass."));
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static cl::opt<bool> EnableStrongPHIElim("strong-phi-elim", cl::Hidden,
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cl::desc("Use strong PHI elimination."));
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static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
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cl::Hidden,
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cl::desc("Disable Machine LICM"));
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static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
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cl::desc("Disable Machine Sinking"));
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static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
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cl::desc("Disable Loop Strength Reduction Pass"));
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static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
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cl::desc("Disable Codegen Prepare"));
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static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
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cl::desc("Disable Copy Propagation pass"));
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static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
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cl::desc("Print LLVM IR produced by the loop-reduce pass"));
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static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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cl::desc("Print LLVM IR input to isel pass"));
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static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
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cl::desc("Dump garbage collector data"));
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static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
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cl::desc("Verify generated machine code"),
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cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
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// Allow Pass selection to be overriden by command line options.
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//
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// DefaultID is the default pass to run which may be NoPassID, or may be
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// overriden by the target.
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//
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// OptionalID is a pass that may be forcibly enabled by the user when the
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// default is NoPassID.
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char &enablePass(char &DefaultID, cl::boolOrDefault Override,
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char *OptionalIDPtr = &NoPassID) {
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switch (Override) {
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case cl::BOU_UNSET:
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return DefaultID;
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case cl::BOU_TRUE:
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if (&DefaultID != &NoPassID)
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return DefaultID;
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if (OptionalIDPtr == &NoPassID)
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report_fatal_error("Target cannot enable pass");
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return *OptionalIDPtr;
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case cl::BOU_FALSE:
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return NoPassID;
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}
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llvm_unreachable("Invalid command line option state");
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}
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//===---------------------------------------------------------------------===//
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/// TargetPassConfig
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//===---------------------------------------------------------------------===//
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INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
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"Target Pass Configuration", false, false)
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char TargetPassConfig::ID = 0;
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static char NoPassIDAnchor = 0;
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char &llvm::NoPassID = NoPassIDAnchor;
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// Out of line virtual method.
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TargetPassConfig::~TargetPassConfig() {}
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// Out of line constructor provides default values for pass options and
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// registers all common codegen passes.
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TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
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: ImmutablePass(ID), TM(tm), PM(pm), Initialized(false),
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DisableVerify(false),
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EnableTailMerge(true) {
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// Register all target independent codegen passes to activate their PassIDs,
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// including this pass itself.
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initializeCodeGen(*PassRegistry::getPassRegistry());
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}
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/// createPassConfig - Create a pass configuration object to be used by
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/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
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///
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/// Targets may override this to extend TargetPassConfig.
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TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new TargetPassConfig(this, PM);
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}
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TargetPassConfig::TargetPassConfig()
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: ImmutablePass(ID), PM(*(PassManagerBase*)0) {
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llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
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}
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// Helper to verify the analysis is really immutable.
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void TargetPassConfig::setOpt(bool &Opt, bool Val) {
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assert(!Initialized && "PassConfig is immutable");
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Opt = Val;
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}
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void TargetPassConfig::addPass(char &ID) {
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if (&ID == &NoPassID)
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return;
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// FIXME: check user overrides
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Pass *P = Pass::createPass(ID);
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if (!P)
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llvm_unreachable("Pass ID not registered");
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PM.add(P);
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}
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void TargetPassConfig::printNoVerify(const char *Banner) const {
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if (TM->shouldPrintMachineCode())
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PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
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}
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void TargetPassConfig::printAndVerify(const char *Banner) const {
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if (TM->shouldPrintMachineCode())
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PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
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if (VerifyMachineCode)
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PM.add(createMachineVerifierPass(Banner));
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}
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/// Add common target configurable passes that perform LLVM IR to IR transforms
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/// following machine independent optimization.
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void TargetPassConfig::addIRPasses() {
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// Basic AliasAnalysis support.
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// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
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// BasicAliasAnalysis wins if they disagree. This is intended to help
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// support "obvious" type-punning idioms.
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PM.add(createTypeBasedAliasAnalysisPass());
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PM.add(createBasicAliasAnalysisPass());
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// Before running any passes, run the verifier to determine if the input
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// coming from the front-end and/or optimizer is valid.
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if (!DisableVerify)
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PM.add(createVerifierPass());
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// Run loop strength reduction before anything else.
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if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
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PM.add(createLoopStrengthReducePass(getTargetLowering()));
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if (PrintLSR)
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PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
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}
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PM.add(createGCLoweringPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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}
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/// Add common passes that perform LLVM IR to IR transforms in preparation for
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/// instruction selection.
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void TargetPassConfig::addISelPrepare() {
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if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
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PM.add(createCodeGenPreparePass(getTargetLowering()));
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PM.add(createStackProtectorPass(getTargetLowering()));
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addPreISel();
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if (PrintISelInput)
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PM.add(createPrintFunctionPass("\n\n"
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"*** Final LLVM Code input to ISel ***\n",
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&dbgs()));
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// All passes which modify the LLVM IR are now complete; run the verifier
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// to ensure that the IR is valid.
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if (!DisableVerify)
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PM.add(createVerifierPass());
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}
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/// Add the complete set of target-independent postISel code generator passes.
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///
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/// This can be read as the standard order of major LLVM CodeGen stages. Stages
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/// with nontrivial configuration or multiple passes are broken out below in
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/// add%Stage routines.
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///
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/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
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/// addPre/Post methods with empty header implementations allow injecting
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/// target-specific fixups just before or after major stages. Additionally,
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/// targets have the flexibility to change pass order within a stage by
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/// overriding default implementation of add%Stage routines below. Each
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/// technique has maintainability tradeoffs because alternate pass orders are
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/// not well supported. addPre/Post works better if the target pass is easily
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/// tied to a common pass. But if it has subtle dependencies on multiple passes,
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/// the target should override the stage instead.
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///
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/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
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/// before/after any target-independent pass. But it's currently overkill.
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void TargetPassConfig::addMachinePasses() {
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// Print the instruction selected machine code...
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printAndVerify("After Instruction Selection");
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// Expand pseudo-instructions emitted by ISel.
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addPass(ExpandISelPseudosID);
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// Add passes that optimize machine instructions in SSA form.
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if (getOptLevel() != CodeGenOpt::None) {
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addMachineSSAOptimization();
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}
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else {
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// If the target requests it, assign local variables to stack slots relative
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// to one another and simplify frame index references where possible.
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addPass(LocalStackSlotAllocationID);
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}
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// Run pre-ra passes.
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if (addPreRegAlloc())
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printAndVerify("After PreRegAlloc passes");
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// Run register allocation and passes that are tightly coupled with it,
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// including phi elimination and scheduling.
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if (getOptimizeRegAlloc())
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addOptimizedRegAlloc(createRegAllocPass(true));
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else
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addFastRegAlloc(createRegAllocPass(false));
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// Run post-ra passes.
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if (addPostRegAlloc())
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printAndVerify("After PostRegAlloc passes");
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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addPass(PrologEpilogCodeInserterID);
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printAndVerify("After PrologEpilogCodeInserter");
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/// Add passes that optimize machine instructions after register allocation.
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if (getOptLevel() != CodeGenOpt::None)
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addMachineLateOptimization();
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// Expand pseudo instructions before second scheduling pass.
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addPass(ExpandPostRAPseudosID);
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printNoVerify("After ExpandPostRAPseudos");
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// Run pre-sched2 passes.
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if (addPreSched2())
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printNoVerify("After PreSched2 passes");
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// Second pass scheduler.
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if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
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addPass(PostRASchedulerID);
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printNoVerify("After PostRAScheduler");
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}
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// GC
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addPass(GCMachineCodeAnalysisID);
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if (PrintGCInfo)
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PM.add(createGCInfoPrinter(dbgs()));
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// Basic block placement.
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if (getOptLevel() != CodeGenOpt::None && !DisableCodePlace)
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addBlockPlacement();
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if (addPreEmitPass())
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printNoVerify("After PreEmit passes");
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}
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/// Add passes that optimize machine instructions in SSA form.
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void TargetPassConfig::addMachineSSAOptimization() {
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// Pre-ra tail duplication.
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if (!DisableEarlyTailDup) {
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addPass(TailDuplicateID);
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printAndVerify("After Pre-RegAlloc TailDuplicate");
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}
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// Optimize PHIs before DCE: removing dead PHI cycles may make more
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// instructions dead.
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addPass(OptimizePHIsID);
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// If the target requests it, assign local variables to stack slots relative
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// to one another and simplify frame index references where possible.
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addPass(LocalStackSlotAllocationID);
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// With optimization, dead code should already be eliminated. However
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// there is one known exception: lowered code for arguments that are only
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// used by tail calls, where the tail calls reuse the incoming stack
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// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
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if (!DisableMachineDCE)
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addPass(DeadMachineInstructionElimID);
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printAndVerify("After codegen DCE pass");
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if (!DisableMachineLICM)
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addPass(MachineLICMID);
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if (!DisableMachineCSE)
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addPass(MachineCSEID);
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if (!DisableMachineSink)
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addPass(MachineSinkingID);
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printAndVerify("After Machine LICM, CSE and Sinking passes");
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addPass(PeepholeOptimizerID);
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printAndVerify("After codegen peephole optimization pass");
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}
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//===---------------------------------------------------------------------===//
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/// Register Allocation Pass Configuration
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//===---------------------------------------------------------------------===//
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bool TargetPassConfig::getOptimizeRegAlloc() const {
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switch (OptimizeRegAlloc) {
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case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
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case cl::BOU_TRUE: return true;
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case cl::BOU_FALSE: return false;
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}
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llvm_unreachable("Invalid optimize-regalloc state");
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}
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/// RegisterRegAlloc's global Registry tracks allocator registration.
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MachinePassRegistry RegisterRegAlloc::Registry;
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/// A dummy default pass factory indicates whether the register allocator is
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/// overridden on the command line.
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static FunctionPass *useDefaultRegisterAllocator() { return 0; }
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static RegisterRegAlloc
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defaultRegAlloc("default",
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"pick register allocator based on -O option",
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useDefaultRegisterAllocator);
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/// -regalloc=... command line option.
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static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
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RegisterPassParser<RegisterRegAlloc> >
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RegAlloc("regalloc",
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cl::init(&useDefaultRegisterAllocator),
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cl::desc("Register allocator to use"));
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/// Instantiate the default register allocator pass for this target for either
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/// the optimized or unoptimized allocation path. This will be added to the pass
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/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
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/// in the optimized case.
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///
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/// A target that uses the standard regalloc pass order for fast or optimized
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/// allocation may still override this for per-target regalloc
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/// selection. But -regalloc=... always takes precedence.
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FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
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if (Optimized)
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return createGreedyRegisterAllocator();
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else
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return createFastRegisterAllocator();
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}
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/// Find and instantiate the register allocation pass requested by this target
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/// at the current optimization level. Different register allocators are
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/// defined as separate passes because they may require different analysis.
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///
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/// This helper ensures that the regalloc= option is always available,
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/// even for targets that override the default allocator.
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///
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/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
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/// this can be folded into addPass.
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FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
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RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
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// Initialize the global default.
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if (!Ctor) {
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Ctor = RegAlloc;
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RegisterRegAlloc::setDefault(RegAlloc);
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}
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if (Ctor != useDefaultRegisterAllocator)
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return Ctor();
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// With no -regalloc= override, ask the target for a regalloc pass.
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return createTargetRegisterAllocator(Optimized);
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}
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/// Add the minimum set of target-independent passes that are required for
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/// register allocation. No coalescing or scheduling.
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void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
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addPass(PHIEliminationID);
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addPass(TwoAddressInstructionPassID);
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PM.add(RegAllocPass);
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printAndVerify("After Register Allocation");
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}
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/// Add standard target-independent passes that are tightly coupled with
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/// optimized register allocation, including coalescing, machine instruction
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/// scheduling, and register allocation itself.
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void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
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// LiveVariables currently requires pure SSA form.
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//
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// FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
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// LiveVariables can be removed completely, and LiveIntervals can be directly
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// computed. (We still either need to regenerate kill flags after regalloc, or
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// preferably fix the scavenger to not depend on them).
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addPass(LiveVariablesID);
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// Add passes that move from transformed SSA into conventional SSA. This is a
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// "copy coalescing" problem.
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//
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if (!EnableStrongPHIElim) {
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// Edge splitting is smarter with machine loop info.
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addPass(MachineLoopInfoID);
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addPass(PHIEliminationID);
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}
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addPass(TwoAddressInstructionPassID);
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// FIXME: Either remove this pass completely, or fix it so that it works on
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// SSA form. We could modify LiveIntervals to be independent of this pass, But
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// it would be even better to simply eliminate *all* IMPLICIT_DEFs before
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// leaving SSA.
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addPass(ProcessImplicitDefsID);
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if (EnableStrongPHIElim)
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addPass(StrongPHIEliminationID);
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addPass(RegisterCoalescerID);
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// PreRA instruction scheduling.
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addPass(enablePass(getSchedPass(), EnableMachineSched, &MachineSchedulerID));
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// Add the selected register allocation pass.
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PM.add(RegAllocPass);
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printAndVerify("After Register Allocation");
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// FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,
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// but eventually, all users of it should probably be moved to addPostRA and
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// it can go away. Currently, it's the intended place for targets to run
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// FinalizeMachineBundles, because passes other than MachineScheduling an
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// RegAlloc itself may not be aware of bundles.
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if (addFinalizeRegAlloc())
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printAndVerify("After RegAlloc finalization");
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|
|
|
// Perform stack slot coloring and post-ra machine LICM.
|
|
//
|
|
// FIXME: Re-enable coloring with register when it's capable of adding
|
|
// kill markers.
|
|
if (!DisableSSC)
|
|
addPass(StackSlotColoringID);
|
|
|
|
// Run post-ra machine LICM to hoist reloads / remats.
|
|
//
|
|
// FIXME: can this move into MachineLateOptimization?
|
|
if (!DisablePostRAMachineLICM)
|
|
addPass(MachineLICMID);
|
|
|
|
printAndVerify("After StackSlotColoring and postra Machine LICM");
|
|
}
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
/// Post RegAlloc Pass Configuration
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
/// Add passes that optimize machine instructions after register allocation.
|
|
void TargetPassConfig::addMachineLateOptimization() {
|
|
// Branch folding must be run after regalloc and prolog/epilog insertion.
|
|
if (!DisableBranchFold) {
|
|
addPass(BranchFolderPassID);
|
|
printNoVerify("After BranchFolding");
|
|
}
|
|
|
|
// Tail duplication.
|
|
if (!DisableTailDuplicate) {
|
|
addPass(TailDuplicateID);
|
|
printNoVerify("After TailDuplicate");
|
|
}
|
|
|
|
// Copy propagation.
|
|
if (!DisableCopyProp) {
|
|
addPass(MachineCopyPropagationID);
|
|
printNoVerify("After copy propagation pass");
|
|
}
|
|
}
|
|
|
|
/// Add standard basic block placement passes.
|
|
void TargetPassConfig::addBlockPlacement() {
|
|
if (EnableBlockPlacement) {
|
|
// MachineBlockPlacement is an experimental pass which is disabled by
|
|
// default currently. Eventually it should subsume CodePlacementOpt, so
|
|
// when enabled, the other is disabled.
|
|
addPass(MachineBlockPlacementID);
|
|
printNoVerify("After MachineBlockPlacement");
|
|
} else {
|
|
addPass(CodePlacementOptID);
|
|
printNoVerify("After CodePlacementOpt");
|
|
}
|
|
|
|
// Run a separate pass to collect block placement statistics.
|
|
if (EnableBlockPlacementStats) {
|
|
addPass(MachineBlockPlacementStatsID);
|
|
printNoVerify("After MachineBlockPlacementStats");
|
|
}
|
|
}
|