llvm-6502/lib/Target/Sparc
Ahmed Bougacha 7fac1d945f [SelectionDAG] Allow targets to specify legality of extloads' result
type (in addition to the memory type).

The *LoadExt* legalization handling used to only have one type, the
memory type.  This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.

However, this isn't always the case.  For instance, on X86, with AVX,
this is legal:
    v4i32 load, zext from v4i8
but this isn't:
    v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.

Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.

Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.

Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior.  The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)

No functional change intended.

Differential Revision: http://reviews.llvm.org/D6532


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225421 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 00:51:32 +00:00
..
AsmParser Minor cleanup to all the switches after MatchInstructionImpl in all the AsmParsers. 2015-01-03 08:16:34 +00:00
Disassembler Pass an ArrayRef to MCDisassembler::getInstruction. 2014-11-12 02:04:27 +00:00
InstPrinter
MCTargetDesc Revert "Use the integrated assembler by default on 32-bit PowerPC and SPARC" 2015-01-05 23:31:51 +00:00
TargetInfo
CMakeLists.txt Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
DelaySlotFiller.cpp
LLVMBuild.txt
Makefile Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
README.txt
Sparc.h Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
Sparc.td
SparcAsmPrinter.cpp
SparcCallingConv.td
SparcFrameLowering.cpp
SparcFrameLowering.h
SparcInstr64Bit.td
SparcInstrAliases.td
SparcInstrFormats.td
SparcInstrInfo.cpp Fix a lot of confusion around inserting nops on empty functions. 2014-09-15 18:32:58 +00:00
SparcInstrInfo.h Fix a lot of confusion around inserting nops on empty functions. 2014-09-15 18:32:58 +00:00
SparcInstrInfo.td
SparcInstrVIS.td
SparcISelDAGToDAG.cpp Cache TargetLowering on SelectionDAGISel and update previous 2014-10-08 07:32:17 +00:00
SparcISelLowering.cpp [SelectionDAG] Allow targets to specify legality of extloads' result 2015-01-08 00:51:32 +00:00
SparcISelLowering.h
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcMCInstLower.cpp
SparcRegisterInfo.cpp
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp
SparcSubtarget.h Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
SparcTargetMachine.cpp [CodeGen] Add print and verify pass after each MachineFunctionPass by default 2014-12-11 21:26:47 +00:00
SparcTargetMachine.h Add out of line virtual destructors to all LLVMTargetMachine subclasses 2014-11-20 23:37:18 +00:00
SparcTargetObjectFile.cpp
SparcTargetObjectFile.h
SparcTargetStreamer.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.