mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-06 09:54:49 +00:00
9de5d0dd42
- Cleaned up custom load/store logic, common code is now shared [see note below], cleaned up address modes - More test cases: various intrinsics, structure element access (load/store test), updated target data strings, indirect function calls. Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode structures: they now share a common base class, LSBaseSDNode, that provides an interface to their common functionality. There is some hackery to access the proper operand depending on the derived class; otherwise, to do a proper job would require finding and rearranging the SDOperands sent to StoreSDNode's constructor. The current refactor errs on the side of being conservatively and backwardly compatible while providing functionality that reduces redundant code for targets where loads and stores are custom-lowered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45851 91177308-0d34-0410-b5e6-96231b3b80d8
213 lines
4.7 KiB
LLVM
213 lines
4.7 KiB
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep shlh %t1.s | count 84
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; RUN: grep shlhi %t1.s | count 51
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; RUN: grep shl %t1.s | count 168
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; RUN: grep shli %t1.s | count 51
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; RUN: grep xshw %t1.s | count 5
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; RUN: grep and %t1.s | count 5
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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; Vector shifts are not currently supported in gcc or llvm assembly. These are
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; not tested.
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; Shift left i16 via register, note that the second operand to shl is promoted
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; to a 32-bit type:
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define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
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%A = shl i16 %arg1, %arg2
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ret i16 %A
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}
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define i16 @shlh_i16_2(i16 %arg1, i16 %arg2) {
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%A = shl i16 %arg2, %arg1
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ret i16 %A
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}
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define i16 @shlh_i16_3(i16 signext %arg1, i16 signext %arg2) signext {
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%A = shl i16 %arg1, %arg2
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ret i16 %A
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}
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define i16 @shlh_i16_4(i16 signext %arg1, i16 signext %arg2) signext {
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%A = shl i16 %arg2, %arg1
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ret i16 %A
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}
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define i16 @shlh_i16_5(i16 zeroext %arg1, i16 zeroext %arg2) zeroext {
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%A = shl i16 %arg1, %arg2
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ret i16 %A
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}
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define i16 @shlh_i16_6(i16 zeroext %arg1, i16 zeroext %arg2) zeroext {
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%A = shl i16 %arg2, %arg1
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ret i16 %A
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}
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; Shift left i16 with immediate:
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define i16 @shlhi_i16_1(i16 %arg1) {
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%A = shl i16 %arg1, 12
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ret i16 %A
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}
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; Should not generate anything other than the return, arg1 << 0 = arg1
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define i16 @shlhi_i16_2(i16 %arg1) {
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%A = shl i16 %arg1, 0
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ret i16 %A
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}
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define i16 @shlhi_i16_3(i16 %arg1) {
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%A = shl i16 16383, %arg1
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ret i16 %A
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}
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; Should generate 0, 0 << arg1 = 0
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define i16 @shlhi_i16_4(i16 %arg1) {
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%A = shl i16 0, %arg1
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ret i16 %A
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}
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define i16 @shlhi_i16_5(i16 signext %arg1) signext {
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%A = shl i16 %arg1, 12
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ret i16 %A
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}
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; Should not generate anything other than the return, arg1 << 0 = arg1
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define i16 @shlhi_i16_6(i16 signext %arg1) signext {
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%A = shl i16 %arg1, 0
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ret i16 %A
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}
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define i16 @shlhi_i16_7(i16 signext %arg1) signext {
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%A = shl i16 16383, %arg1
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ret i16 %A
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}
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; Should generate 0, 0 << arg1 = 0
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define i16 @shlhi_i16_8(i16 signext %arg1) signext {
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%A = shl i16 0, %arg1
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ret i16 %A
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}
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define i16 @shlhi_i16_9(i16 zeroext %arg1) zeroext {
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%A = shl i16 %arg1, 12
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ret i16 %A
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}
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; Should not generate anything other than the return, arg1 << 0 = arg1
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define i16 @shlhi_i16_10(i16 zeroext %arg1) zeroext {
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%A = shl i16 %arg1, 0
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ret i16 %A
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}
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define i16 @shlhi_i16_11(i16 zeroext %arg1) zeroext {
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%A = shl i16 16383, %arg1
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ret i16 %A
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}
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; Should generate 0, 0 << arg1 = 0
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define i16 @shlhi_i16_12(i16 zeroext %arg1) zeroext {
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%A = shl i16 0, %arg1
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ret i16 %A
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}
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; Shift left i32 via register, note that the second operand to shl is promoted
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; to a 32-bit type:
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define i32 @shl_i32_1(i32 %arg1, i32 %arg2) {
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%A = shl i32 %arg1, %arg2
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ret i32 %A
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}
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define i32 @shl_i32_2(i32 %arg1, i32 %arg2) {
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%A = shl i32 %arg2, %arg1
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ret i32 %A
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}
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define i32 @shl_i32_3(i32 signext %arg1, i32 signext %arg2) signext {
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%A = shl i32 %arg1, %arg2
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ret i32 %A
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}
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define i32 @shl_i32_4(i32 signext %arg1, i32 signext %arg2) signext {
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%A = shl i32 %arg2, %arg1
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ret i32 %A
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}
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define i32 @shl_i32_5(i32 zeroext %arg1, i32 zeroext %arg2) zeroext {
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%A = shl i32 %arg1, %arg2
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ret i32 %A
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}
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define i32 @shl_i32_6(i32 zeroext %arg1, i32 zeroext %arg2) zeroext {
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%A = shl i32 %arg2, %arg1
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ret i32 %A
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}
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; Shift left i32 with immediate:
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define i32 @shli_i32_1(i32 %arg1) {
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%A = shl i32 %arg1, 12
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ret i32 %A
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}
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; Should not generate anything other than the return, arg1 << 0 = arg1
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define i32 @shli_i32_2(i32 %arg1) {
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%A = shl i32 %arg1, 0
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ret i32 %A
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}
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define i32 @shli_i32_3(i32 %arg1) {
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%A = shl i32 16383, %arg1
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ret i32 %A
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}
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; Should generate 0, 0 << arg1 = 0
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define i32 @shli_i32_4(i32 %arg1) {
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%A = shl i32 0, %arg1
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ret i32 %A
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}
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define i32 @shli_i32_5(i32 signext %arg1) signext {
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%A = shl i32 %arg1, 12
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ret i32 %A
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}
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; Should not generate anything other than the return, arg1 << 0 = arg1
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define i32 @shli_i32_6(i32 signext %arg1) signext {
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%A = shl i32 %arg1, 0
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ret i32 %A
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}
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define i32 @shli_i32_7(i32 signext %arg1) signext {
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%A = shl i32 16383, %arg1
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ret i32 %A
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}
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; Should generate 0, 0 << arg1 = 0
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define i32 @shli_i32_8(i32 signext %arg1) signext {
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%A = shl i32 0, %arg1
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ret i32 %A
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}
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define i32 @shli_i32_9(i32 zeroext %arg1) zeroext {
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%A = shl i32 %arg1, 12
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ret i32 %A
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}
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; Should not generate anything other than the return, arg1 << 0 = arg1
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define i32 @shli_i32_10(i32 zeroext %arg1) zeroext {
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%A = shl i32 %arg1, 0
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ret i32 %A
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}
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define i32 @shli_i32_11(i32 zeroext %arg1) zeroext {
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%A = shl i32 16383, %arg1
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ret i32 %A
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}
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; Should generate 0, 0 << arg1 = 0
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define i32 @shli_i32_12(i32 zeroext %arg1) zeroext {
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%A = shl i32 0, %arg1
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ret i32 %A
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}
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