mirror of
https://github.com/c64scene-ar/llvm-6502.git
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13c782674a
Summary: x86 allows either ordering for the LOCK and DATA16 prefixes, but using GCC+GAS leads to different code generation than using LLVM. This change matches the order that GAS emits the x86 prefixes when a semicolon isn't used in inline assembly (see tc-i386.c comment before define LOCK_PREFIX), and helps simplify tooling that operates on the instruction's byte sequence (such as NaCl's validator). This change shouldn't have any performance impact. Test Plan: ninja check Reviewers: craig.topper, jvoung Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D6630 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224283 91177308-0d34-0410-b5e6-96231b3b80d8
268 lines
6.1 KiB
LLVM
268 lines
6.1 KiB
LLVM
; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mcpu=corei7 -verify-machineinstrs -show-mc-encoding | FileCheck %s --check-prefix X64
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; RUN: llc < %s -O0 -mtriple=i386-unknown-unknown -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X32
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@sc16 = external global i16
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define void @atomic_fetch_add16() nounwind {
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; X64-LABEL: atomic_fetch_add16
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; X32-LABEL: atomic_fetch_add16
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entry:
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; 32-bit
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%t1 = atomicrmw add i16* @sc16, i16 1 acquire
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; X64: lock
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; X64: incw
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; X32: lock
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; X32: incw
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%t2 = atomicrmw add i16* @sc16, i16 3 acquire
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; X64: lock
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; X64: addw $3, {{.*}} # encoding: [0x66,0xf0
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; X32: lock
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; X32: addw $3
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%t3 = atomicrmw add i16* @sc16, i16 5 acquire
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; X64: lock
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; X64: xaddw {{.*}} # encoding: [0x66,0xf0
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; X32: lock
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; X32: xaddw
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%t4 = atomicrmw add i16* @sc16, i16 %t3 acquire
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; X64: lock
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; X64: addw {{.*}} # encoding: [0x66,0xf0
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; X32: lock
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; X32: addw
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_sub16() nounwind {
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; X64-LABEL: atomic_fetch_sub16
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; X32-LABEL: atomic_fetch_sub16
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%t1 = atomicrmw sub i16* @sc16, i16 1 acquire
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; X64: lock
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; X64: decw
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; X32: lock
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; X32: decw
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%t2 = atomicrmw sub i16* @sc16, i16 3 acquire
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; X64: lock
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; X64: subw $3, {{.*}} # encoding: [0x66,0xf0
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; X32: lock
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; X32: subw $3
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%t3 = atomicrmw sub i16* @sc16, i16 5 acquire
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; X64: lock
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; X64: xaddw {{.*}} # encoding: [0x66,0xf0
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; X32: lock
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; X32: xaddw
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%t4 = atomicrmw sub i16* @sc16, i16 %t3 acquire
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; X64: lock
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; X64: subw {{.*}} # encoding: [0x66,0xf0
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; X32: lock
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; X32: subw
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_and16() nounwind {
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; X64-LABEL: atomic_fetch_and16
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; X32-LABEL: atomic_fetch_and16
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%t1 = atomicrmw and i16* @sc16, i16 3 acquire
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; X64: lock
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; X64: andw $3, {{.*}} # encoding: [0x66,0xf0
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; X32: lock
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; X32: andw $3
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%t2 = atomicrmw and i16* @sc16, i16 5 acquire
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; X64: andl
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; X64: lock
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; X64: cmpxchgw
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; X32: andl
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; X32: lock
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; X32: cmpxchgw
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%t3 = atomicrmw and i16* @sc16, i16 %t2 acquire
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; X64: lock
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; X64: andw {{.*}} # encoding: [0x66,0xf0
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; X32: lock
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; X32: andw
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_or16() nounwind {
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; X64-LABEL: atomic_fetch_or16
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; X32-LABEL: atomic_fetch_or16
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%t1 = atomicrmw or i16* @sc16, i16 3 acquire
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; X64: lock
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; X64: orw $3, {{.*}} # encoding: [0x66,0xf0
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; X32: lock
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; X32: orw $3
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%t2 = atomicrmw or i16* @sc16, i16 5 acquire
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; X64: orl
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; X64: lock
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; X64: cmpxchgw
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; X32: orl
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; X32: lock
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; X32: cmpxchgw
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%t3 = atomicrmw or i16* @sc16, i16 %t2 acquire
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; X64: lock
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; X64: orw {{.*}} # encoding: [0x66,0xf0
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; X32: lock
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; X32: orw
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_xor16() nounwind {
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; X64-LABEL: atomic_fetch_xor16
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; X32-LABEL: atomic_fetch_xor16
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%t1 = atomicrmw xor i16* @sc16, i16 3 acquire
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; X64: lock
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; X64: xorw $3, {{.*}} # encoding: [0x66,0xf0
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; X32: lock
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; X32: xorw $3
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%t2 = atomicrmw xor i16* @sc16, i16 5 acquire
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; X64: xorl
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; X64: lock
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; X64: cmpxchgw
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; X32: xorl
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; X32: lock
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; X32: cmpxchgw
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%t3 = atomicrmw xor i16* @sc16, i16 %t2 acquire
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; X64: lock
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; X64: xorw {{.*}} # encoding: [0x66,0xf0
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; X32: lock
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; X32: xorw
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_nand16(i16 %x) nounwind {
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; X64-LABEL: atomic_fetch_nand16
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; X32-LABEL: atomic_fetch_nand16
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%t1 = atomicrmw nand i16* @sc16, i16 %x acquire
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; X64: andl
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; X64: notl
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; X64: lock
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; X64: cmpxchgw
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; X32: andl
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; X32: notl
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; X32: lock
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; X32: cmpxchgw
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_max16(i16 %x) nounwind {
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%t1 = atomicrmw max i16* @sc16, i16 %x acquire
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; X64: movswl
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; X64: movswl
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; X64: subl
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; X64: cmov
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; X64: lock
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; X64: cmpxchgw
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; X32: movswl
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; X32: movswl
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; X32: subl
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; X32: cmov
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; X32: lock
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; X32: cmpxchgw
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_min16(i16 %x) nounwind {
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%t1 = atomicrmw min i16* @sc16, i16 %x acquire
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; X64: movswl
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; X64: movswl
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; X64: subl
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; X64: cmov
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; X64: lock
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; X64: cmpxchgw
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; X32: movswl
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; X32: movswl
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; X32: subl
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; X32: cmov
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; X32: lock
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; X32: cmpxchgw
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_umax16(i16 %x) nounwind {
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%t1 = atomicrmw umax i16* @sc16, i16 %x acquire
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; X64: movzwl
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; X64: movzwl
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; X64: subl
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; X64: cmov
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; X64: lock
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; X64: cmpxchgw
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; X32: movzwl
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; X32: movzwl
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; X32: subl
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; X32: cmov
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; X32: lock
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; X32: cmpxchgw
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_umin16(i16 %x) nounwind {
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%t1 = atomicrmw umin i16* @sc16, i16 %x acquire
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; X64: movzwl
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; X64: movzwl
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; X64: subl
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; X64: cmov
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; X64: lock
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; X64: cmpxchgw
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; X32: movzwl
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; X32: movzwl
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; X32: subl
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; X32: cmov
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; X32: lock
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; X32: cmpxchgw
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_cmpxchg16() nounwind {
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%t1 = cmpxchg i16* @sc16, i16 0, i16 1 acquire acquire
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; X64: lock
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; X64: cmpxchgw
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; X32: lock
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; X32: cmpxchgw
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_store16(i16 %x) nounwind {
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store atomic i16 %x, i16* @sc16 release, align 4
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; X64-NOT: lock
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; X64: movw
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; X32-NOT: lock
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; X32: movw
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_swap16(i16 %x) nounwind {
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%t1 = atomicrmw xchg i16* @sc16, i16 %x acquire
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; X64-NOT: lock
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; X64: xchgw
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; X32-NOT: lock
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; X32: xchgw
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ret void
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; X64: ret
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; X32: ret
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}
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