Hal Finkel cd9ea51986 Expand PPC64 atomic load and store ... Use of store or load with the atomic specifier on 64-bit types would cause instruction-selection failures. As with the 32-bit case, these can use the default expansion in terms of cmp-and-swap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171072 91177308-0d34-0410-b5e6-96231b3b80d8		2012-12-25 17:22:53 +00:00
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ARM	Revert "Adding support for llvm.arm.neon.vaddl[su].* and"	2012-12-20 21:09:38 +00:00
CPP
Generic	After reducing the size of an operation in the DAG we zero-extend the reduced	2012-12-19 07:39:08 +00:00
Hexagon
MBlaze
Mips	Add test case for r170674	2012-12-21 00:55:10 +00:00
MSP430
NVPTX
PowerPC	Expand PPC64 atomic load and store	2012-12-25 17:22:53 +00:00
R600	R600: Expand vec4 INT <-> FP conversions	2012-12-21 16:33:24 +00:00
SI
SPARC
Thumb
Thumb2	On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,	2012-12-20 19:59:30 +00:00
X86	Harden test so it's not affected by changes to compare lowering.	2012-12-25 13:23:23 +00:00
XCore