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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-20 11:29:24 +00:00
64d80e3387
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
99 lines
2.8 KiB
C++
99 lines
2.8 KiB
C++
//===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Bruno Cardoso Lopes and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Describe MIPS instructions format
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//
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// All the possible Mips fields are:
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//
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// opcode - operation code.
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// rs - src reg.
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// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
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// rd - dst reg, only used on 3 regs instr.
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// shamt - only used on shift instructions, contains the shift amount.
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// funct - combined with opcode field give us an operation code.
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//
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//===----------------------------------------------------------------------===//
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// Generic Mips Format
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class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern>:
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Instruction
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{
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field bits<32> Inst;
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let Namespace = "Mips";
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bits<6> opcode;
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// Top 5 bits are the 'opcode' field
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let Inst{31-26} = opcode;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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//===----------------------------------------------------------------------===//
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// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
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//===----------------------------------------------------------------------===//
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class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
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list<dag> pattern>:
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MipsInst<outs, ins, asmstr, pattern>
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{
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<5> shamt;
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bits<6> funct;
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let opcode = op;
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let funct = _funct;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = shamt;
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let Inst{5-0} = funct;
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}
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//===----------------------------------------------------------------------===//
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// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
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//===----------------------------------------------------------------------===//
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class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsInst<outs, ins, asmstr, pattern>
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{
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bits<5> rt;
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bits<5> rs;
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bits<16> imm16;
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let opcode = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm16;
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}
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//===----------------------------------------------------------------------===//
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// Format J instruction class in Mips : <|opcode|address|>
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//===----------------------------------------------------------------------===//
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class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsInst<outs, ins, asmstr, pattern>
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{
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bits<26> addr;
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let opcode = op;
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let Inst{25-0} = addr;
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}
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