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utils/sort_includes.py. I clearly haven't done this in a while, so more changed than usual. This even uncovered a missing include from the InstrProf library that I've added. No functionality changed here, just mechanical cleanup of the include order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225974 91177308-0d34-0410-b5e6-96231b3b80d8
953 lines
31 KiB
C++
953 lines
31 KiB
C++
//==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides an interface for customizing the standard MachineScheduler
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// pass. Note that the entire pass may be replaced as follows:
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//
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// <Target>TargetMachine::createPassConfig(PassManagerBase &PM) {
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// PM.substitutePass(&MachineSchedulerID, &CustomSchedulerPassID);
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// ...}
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//
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// The MachineScheduler pass is only responsible for choosing the regions to be
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// scheduled. Targets can override the DAG builder and scheduler without
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// replacing the pass as follows:
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//
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// ScheduleDAGInstrs *<Target>PassConfig::
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// createMachineScheduler(MachineSchedContext *C) {
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// return new CustomMachineScheduler(C);
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// }
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//
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// The default scheduler, ScheduleDAGMILive, builds the DAG and drives list
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// scheduling while updating the instruction stream, register pressure, and live
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// intervals. Most targets don't need to override the DAG builder and list
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// schedulier, but subtargets that require custom scheduling heuristics may
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// plugin an alternate MachineSchedStrategy. The strategy is responsible for
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// selecting the highest priority node from the list:
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//
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// ScheduleDAGInstrs *<Target>PassConfig::
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// createMachineScheduler(MachineSchedContext *C) {
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// return new ScheduleDAGMI(C, CustomStrategy(C));
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// }
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//
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// The DAG builder can also be customized in a sense by adding DAG mutations
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// that will run after DAG building and before list scheduling. DAG mutations
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// can adjust dependencies based on target-specific knowledge or add weak edges
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// to aid heuristics:
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//
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// ScheduleDAGInstrs *<Target>PassConfig::
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// createMachineScheduler(MachineSchedContext *C) {
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// ScheduleDAGMI *DAG = new ScheduleDAGMI(C, CustomStrategy(C));
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// DAG->addMutation(new CustomDependencies(DAG->TII, DAG->TRI));
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// return DAG;
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// }
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//
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// A target that supports alternative schedulers can use the
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// MachineSchedRegistry to allow command line selection. This can be done by
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// implementing the following boilerplate:
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//
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// static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext *C) {
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// return new CustomMachineScheduler(C);
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// }
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// static MachineSchedRegistry
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// SchedCustomRegistry("custom", "Run my target's custom scheduler",
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// createCustomMachineSched);
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//
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//
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// Finally, subtargets that don't need to implement custom heuristics but would
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// like to configure the GenericScheduler's policy for a given scheduler region,
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// including scheduling direction and register pressure tracking policy, can do
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// this:
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//
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// void <SubTarget>Subtarget::
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// overrideSchedPolicy(MachineSchedPolicy &Policy,
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// MachineInstr *begin,
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// MachineInstr *end,
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// unsigned NumRegionInstrs) const {
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// Policy.<Flag> = true;
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// }
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINESCHEDULER_H
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#define LLVM_CODEGEN_MACHINESCHEDULER_H
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#include "llvm/CodeGen/MachinePassRegistry.h"
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#include "llvm/CodeGen/RegisterPressure.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include <memory>
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namespace llvm {
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extern cl::opt<bool> ForceTopDown;
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extern cl::opt<bool> ForceBottomUp;
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class AliasAnalysis;
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class LiveIntervals;
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class MachineDominatorTree;
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class MachineLoopInfo;
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class RegisterClassInfo;
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class ScheduleDAGInstrs;
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class SchedDFSResult;
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class ScheduleHazardRecognizer;
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/// MachineSchedContext provides enough context from the MachineScheduler pass
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/// for the target to instantiate a scheduler.
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struct MachineSchedContext {
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MachineFunction *MF;
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const MachineLoopInfo *MLI;
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const MachineDominatorTree *MDT;
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const TargetPassConfig *PassConfig;
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AliasAnalysis *AA;
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LiveIntervals *LIS;
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RegisterClassInfo *RegClassInfo;
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MachineSchedContext();
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virtual ~MachineSchedContext();
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};
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/// MachineSchedRegistry provides a selection of available machine instruction
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/// schedulers.
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class MachineSchedRegistry : public MachinePassRegistryNode {
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public:
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typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *);
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// RegisterPassParser requires a (misnamed) FunctionPassCtor type.
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typedef ScheduleDAGCtor FunctionPassCtor;
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static MachinePassRegistry Registry;
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MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
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: MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
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Registry.Add(this);
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}
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~MachineSchedRegistry() { Registry.Remove(this); }
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// Accessors.
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//
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MachineSchedRegistry *getNext() const {
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return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
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}
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static MachineSchedRegistry *getList() {
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return (MachineSchedRegistry *)Registry.getList();
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}
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static void setListener(MachinePassRegistryListener *L) {
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Registry.setListener(L);
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}
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};
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class ScheduleDAGMI;
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/// Define a generic scheduling policy for targets that don't provide their own
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/// MachineSchedStrategy. This can be overriden for each scheduling region
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/// before building the DAG.
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struct MachineSchedPolicy {
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// Allow the scheduler to disable register pressure tracking.
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bool ShouldTrackPressure;
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// Allow the scheduler to force top-down or bottom-up scheduling. If neither
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// is true, the scheduler runs in both directions and converges.
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bool OnlyTopDown;
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bool OnlyBottomUp;
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MachineSchedPolicy(): ShouldTrackPressure(false), OnlyTopDown(false),
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OnlyBottomUp(false) {}
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};
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/// MachineSchedStrategy - Interface to the scheduling algorithm used by
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/// ScheduleDAGMI.
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///
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/// Initialization sequence:
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/// initPolicy -> shouldTrackPressure -> initialize(DAG) -> registerRoots
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class MachineSchedStrategy {
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virtual void anchor();
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public:
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virtual ~MachineSchedStrategy() {}
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/// Optionally override the per-region scheduling policy.
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virtual void initPolicy(MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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unsigned NumRegionInstrs) {}
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/// Check if pressure tracking is needed before building the DAG and
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/// initializing this strategy. Called after initPolicy.
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virtual bool shouldTrackPressure() const { return true; }
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/// Initialize the strategy after building the DAG for a new region.
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virtual void initialize(ScheduleDAGMI *DAG) = 0;
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/// Notify this strategy that all roots have been released (including those
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/// that depend on EntrySU or ExitSU).
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virtual void registerRoots() {}
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/// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
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/// schedule the node at the top of the unscheduled region. Otherwise it will
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/// be scheduled at the bottom.
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virtual SUnit *pickNode(bool &IsTopNode) = 0;
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/// \brief Scheduler callback to notify that a new subtree is scheduled.
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virtual void scheduleTree(unsigned SubtreeID) {}
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/// Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an
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/// instruction and updated scheduled/remaining flags in the DAG nodes.
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virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
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/// When all predecessor dependencies have been resolved, free this node for
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/// top-down scheduling.
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virtual void releaseTopNode(SUnit *SU) = 0;
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/// When all successor dependencies have been resolved, free this node for
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/// bottom-up scheduling.
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virtual void releaseBottomNode(SUnit *SU) = 0;
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};
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/// Mutate the DAG as a postpass after normal DAG building.
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class ScheduleDAGMutation {
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virtual void anchor();
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public:
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virtual ~ScheduleDAGMutation() {}
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virtual void apply(ScheduleDAGMI *DAG) = 0;
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};
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/// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply
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/// schedules machine instructions according to the given MachineSchedStrategy
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/// without much extra book-keeping. This is the common functionality between
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/// PreRA and PostRA MachineScheduler.
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class ScheduleDAGMI : public ScheduleDAGInstrs {
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protected:
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AliasAnalysis *AA;
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std::unique_ptr<MachineSchedStrategy> SchedImpl;
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/// Topo - A topological ordering for SUnits which permits fast IsReachable
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/// and similar queries.
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ScheduleDAGTopologicalSort Topo;
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/// Ordered list of DAG postprocessing steps.
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std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
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/// The top of the unscheduled zone.
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MachineBasicBlock::iterator CurrentTop;
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/// The bottom of the unscheduled zone.
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MachineBasicBlock::iterator CurrentBottom;
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/// Record the next node in a scheduled cluster.
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const SUnit *NextClusterPred;
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const SUnit *NextClusterSucc;
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#ifndef NDEBUG
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/// The number of instructions scheduled so far. Used to cut off the
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/// scheduler at the point determined by misched-cutoff.
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unsigned NumInstrsScheduled;
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#endif
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public:
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ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
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bool IsPostRA)
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: ScheduleDAGInstrs(*C->MF, C->MLI, IsPostRA,
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/*RemoveKillFlags=*/IsPostRA, C->LIS),
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AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(),
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CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) {
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#ifndef NDEBUG
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NumInstrsScheduled = 0;
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#endif
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}
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// Provide a vtable anchor
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~ScheduleDAGMI() override;
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/// Return true if this DAG supports VReg liveness and RegPressure.
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virtual bool hasVRegLiveness() const { return false; }
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/// Add a postprocessing step to the DAG builder.
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/// Mutations are applied in the order that they are added after normal DAG
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/// building and before MachineSchedStrategy initialization.
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///
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/// ScheduleDAGMI takes ownership of the Mutation object.
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void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) {
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Mutations.push_back(std::move(Mutation));
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}
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/// \brief True if an edge can be added from PredSU to SuccSU without creating
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/// a cycle.
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bool canAddEdge(SUnit *SuccSU, SUnit *PredSU);
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/// \brief Add a DAG edge to the given SU with the given predecessor
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/// dependence data.
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///
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/// \returns true if the edge may be added without creating a cycle OR if an
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/// equivalent edge already existed (false indicates failure).
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bool addEdge(SUnit *SuccSU, const SDep &PredDep);
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MachineBasicBlock::iterator top() const { return CurrentTop; }
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MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
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/// Implement the ScheduleDAGInstrs interface for handling the next scheduling
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/// region. This covers all instructions in a block, while schedule() may only
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/// cover a subset.
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void enterRegion(MachineBasicBlock *bb,
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MachineBasicBlock::iterator begin,
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MachineBasicBlock::iterator end,
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unsigned regioninstrs) override;
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/// Implement ScheduleDAGInstrs interface for scheduling a sequence of
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/// reorderable instructions.
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void schedule() override;
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/// Change the position of an instruction within the basic block and update
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/// live ranges and region boundary iterators.
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void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
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const SUnit *getNextClusterPred() const { return NextClusterPred; }
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const SUnit *getNextClusterSucc() const { return NextClusterSucc; }
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void viewGraph(const Twine &Name, const Twine &Title) override;
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void viewGraph() override;
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protected:
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// Top-Level entry points for the schedule() driver...
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/// Apply each ScheduleDAGMutation step in order. This allows different
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/// instances of ScheduleDAGMI to perform custom DAG postprocessing.
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void postprocessDAG();
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/// Release ExitSU predecessors and setup scheduler queues.
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void initQueues(ArrayRef<SUnit*> TopRoots, ArrayRef<SUnit*> BotRoots);
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/// Update scheduler DAG and queues after scheduling an instruction.
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void updateQueues(SUnit *SU, bool IsTopNode);
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/// Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
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void placeDebugValues();
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/// \brief dump the scheduled Sequence.
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void dumpSchedule() const;
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// Lesser helpers...
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bool checkSchedLimit();
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void findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
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SmallVectorImpl<SUnit*> &BotRoots);
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void releaseSucc(SUnit *SU, SDep *SuccEdge);
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void releaseSuccessors(SUnit *SU);
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void releasePred(SUnit *SU, SDep *PredEdge);
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void releasePredecessors(SUnit *SU);
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};
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/// ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules
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/// machine instructions while updating LiveIntervals and tracking regpressure.
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class ScheduleDAGMILive : public ScheduleDAGMI {
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protected:
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RegisterClassInfo *RegClassInfo;
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/// Information about DAG subtrees. If DFSResult is NULL, then SchedulerTrees
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/// will be empty.
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SchedDFSResult *DFSResult;
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BitVector ScheduledTrees;
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MachineBasicBlock::iterator LiveRegionEnd;
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// Map each SU to its summary of pressure changes. This array is updated for
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// liveness during bottom-up scheduling. Top-down scheduling may proceed but
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// has no affect on the pressure diffs.
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PressureDiffs SUPressureDiffs;
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/// Register pressure in this region computed by initRegPressure.
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bool ShouldTrackPressure;
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IntervalPressure RegPressure;
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RegPressureTracker RPTracker;
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/// List of pressure sets that exceed the target's pressure limit before
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/// scheduling, listed in increasing set ID order. Each pressure set is paired
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/// with its max pressure in the currently scheduled regions.
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std::vector<PressureChange> RegionCriticalPSets;
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/// The top of the unscheduled zone.
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IntervalPressure TopPressure;
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RegPressureTracker TopRPTracker;
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/// The bottom of the unscheduled zone.
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IntervalPressure BotPressure;
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RegPressureTracker BotRPTracker;
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public:
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ScheduleDAGMILive(MachineSchedContext *C,
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std::unique_ptr<MachineSchedStrategy> S)
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: ScheduleDAGMI(C, std::move(S), /*IsPostRA=*/false),
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RegClassInfo(C->RegClassInfo), DFSResult(nullptr),
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ShouldTrackPressure(false), RPTracker(RegPressure),
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TopRPTracker(TopPressure), BotRPTracker(BotPressure) {}
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virtual ~ScheduleDAGMILive();
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/// Return true if this DAG supports VReg liveness and RegPressure.
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bool hasVRegLiveness() const override { return true; }
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/// \brief Return true if register pressure tracking is enabled.
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bool isTrackingPressure() const { return ShouldTrackPressure; }
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/// Get current register pressure for the top scheduled instructions.
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const IntervalPressure &getTopPressure() const { return TopPressure; }
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const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
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/// Get current register pressure for the bottom scheduled instructions.
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const IntervalPressure &getBotPressure() const { return BotPressure; }
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const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
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/// Get register pressure for the entire scheduling region before scheduling.
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const IntervalPressure &getRegPressure() const { return RegPressure; }
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const std::vector<PressureChange> &getRegionCriticalPSets() const {
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return RegionCriticalPSets;
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}
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PressureDiff &getPressureDiff(const SUnit *SU) {
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return SUPressureDiffs[SU->NodeNum];
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}
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/// Compute a DFSResult after DAG building is complete, and before any
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/// queue comparisons.
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void computeDFSResult();
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/// Return a non-null DFS result if the scheduling strategy initialized it.
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const SchedDFSResult *getDFSResult() const { return DFSResult; }
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BitVector &getScheduledTrees() { return ScheduledTrees; }
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/// Implement the ScheduleDAGInstrs interface for handling the next scheduling
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/// region. This covers all instructions in a block, while schedule() may only
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/// cover a subset.
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void enterRegion(MachineBasicBlock *bb,
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MachineBasicBlock::iterator begin,
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MachineBasicBlock::iterator end,
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unsigned regioninstrs) override;
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/// Implement ScheduleDAGInstrs interface for scheduling a sequence of
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/// reorderable instructions.
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void schedule() override;
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/// Compute the cyclic critical path through the DAG.
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unsigned computeCyclicCriticalPath();
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protected:
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// Top-Level entry points for the schedule() driver...
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/// Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking
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/// enabled. This sets up three trackers. RPTracker will cover the entire DAG
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/// region, TopTracker and BottomTracker will be initialized to the top and
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/// bottom of the DAG region without covereing any unscheduled instruction.
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void buildDAGWithRegPressure();
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/// Move an instruction and update register pressure.
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void scheduleMI(SUnit *SU, bool IsTopNode);
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// Lesser helpers...
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void initRegPressure();
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void updatePressureDiffs(ArrayRef<unsigned> LiveUses);
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void updateScheduledPressure(const SUnit *SU,
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const std::vector<unsigned> &NewMaxPressure);
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};
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//===----------------------------------------------------------------------===//
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///
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/// Helpers for implementing custom MachineSchedStrategy classes. These take
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/// care of the book-keeping associated with list scheduling heuristics.
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///
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//===----------------------------------------------------------------------===//
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/// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
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/// methods for pushing and removing nodes. ReadyQueue's are uniquely identified
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/// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in.
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///
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/// This is a convenience class that may be used by implementations of
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/// MachineSchedStrategy.
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class ReadyQueue {
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unsigned ID;
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std::string Name;
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std::vector<SUnit*> Queue;
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public:
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ReadyQueue(unsigned id, const Twine &name): ID(id), Name(name.str()) {}
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unsigned getID() const { return ID; }
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StringRef getName() const { return Name; }
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// SU is in this queue if it's NodeQueueID is a superset of this ID.
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bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
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bool empty() const { return Queue.empty(); }
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void clear() { Queue.clear(); }
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unsigned size() const { return Queue.size(); }
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typedef std::vector<SUnit*>::iterator iterator;
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iterator begin() { return Queue.begin(); }
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iterator end() { return Queue.end(); }
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ArrayRef<SUnit*> elements() { return Queue; }
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iterator find(SUnit *SU) {
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return std::find(Queue.begin(), Queue.end(), SU);
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}
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void push(SUnit *SU) {
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Queue.push_back(SU);
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SU->NodeQueueId |= ID;
|
|
}
|
|
|
|
iterator remove(iterator I) {
|
|
(*I)->NodeQueueId &= ~ID;
|
|
*I = Queue.back();
|
|
unsigned idx = I - Queue.begin();
|
|
Queue.pop_back();
|
|
return Queue.begin() + idx;
|
|
}
|
|
|
|
void dump();
|
|
};
|
|
|
|
/// Summarize the unscheduled region.
|
|
struct SchedRemainder {
|
|
// Critical path through the DAG in expected latency.
|
|
unsigned CriticalPath;
|
|
unsigned CyclicCritPath;
|
|
|
|
// Scaled count of micro-ops left to schedule.
|
|
unsigned RemIssueCount;
|
|
|
|
bool IsAcyclicLatencyLimited;
|
|
|
|
// Unscheduled resources
|
|
SmallVector<unsigned, 16> RemainingCounts;
|
|
|
|
void reset() {
|
|
CriticalPath = 0;
|
|
CyclicCritPath = 0;
|
|
RemIssueCount = 0;
|
|
IsAcyclicLatencyLimited = false;
|
|
RemainingCounts.clear();
|
|
}
|
|
|
|
SchedRemainder() { reset(); }
|
|
|
|
void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
|
|
};
|
|
|
|
/// Each Scheduling boundary is associated with ready queues. It tracks the
|
|
/// current cycle in the direction of movement, and maintains the state
|
|
/// of "hazards" and other interlocks at the current cycle.
|
|
class SchedBoundary {
|
|
public:
|
|
/// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
|
|
enum {
|
|
TopQID = 1,
|
|
BotQID = 2,
|
|
LogMaxQID = 2
|
|
};
|
|
|
|
ScheduleDAGMI *DAG;
|
|
const TargetSchedModel *SchedModel;
|
|
SchedRemainder *Rem;
|
|
|
|
ReadyQueue Available;
|
|
ReadyQueue Pending;
|
|
|
|
ScheduleHazardRecognizer *HazardRec;
|
|
|
|
private:
|
|
/// True if the pending Q should be checked/updated before scheduling another
|
|
/// instruction.
|
|
bool CheckPending;
|
|
|
|
// For heuristics, keep a list of the nodes that immediately depend on the
|
|
// most recently scheduled node.
|
|
SmallPtrSet<const SUnit*, 8> NextSUs;
|
|
|
|
/// Number of cycles it takes to issue the instructions scheduled in this
|
|
/// zone. It is defined as: scheduled-micro-ops / issue-width + stalls.
|
|
/// See getStalls().
|
|
unsigned CurrCycle;
|
|
|
|
/// Micro-ops issued in the current cycle
|
|
unsigned CurrMOps;
|
|
|
|
/// MinReadyCycle - Cycle of the soonest available instruction.
|
|
unsigned MinReadyCycle;
|
|
|
|
// The expected latency of the critical path in this scheduled zone.
|
|
unsigned ExpectedLatency;
|
|
|
|
// The latency of dependence chains leading into this zone.
|
|
// For each node scheduled bottom-up: DLat = max DLat, N.Depth.
|
|
// For each cycle scheduled: DLat -= 1.
|
|
unsigned DependentLatency;
|
|
|
|
/// Count the scheduled (issued) micro-ops that can be retired by
|
|
/// time=CurrCycle assuming the first scheduled instr is retired at time=0.
|
|
unsigned RetiredMOps;
|
|
|
|
// Count scheduled resources that have been executed. Resources are
|
|
// considered executed if they become ready in the time that it takes to
|
|
// saturate any resource including the one in question. Counts are scaled
|
|
// for direct comparison with other resources. Counts can be compared with
|
|
// MOps * getMicroOpFactor and Latency * getLatencyFactor.
|
|
SmallVector<unsigned, 16> ExecutedResCounts;
|
|
|
|
/// Cache the max count for a single resource.
|
|
unsigned MaxExecutedResCount;
|
|
|
|
// Cache the critical resources ID in this scheduled zone.
|
|
unsigned ZoneCritResIdx;
|
|
|
|
// Is the scheduled region resource limited vs. latency limited.
|
|
bool IsResourceLimited;
|
|
|
|
// Record the highest cycle at which each resource has been reserved by a
|
|
// scheduled instruction.
|
|
SmallVector<unsigned, 16> ReservedCycles;
|
|
|
|
#ifndef NDEBUG
|
|
// Remember the greatest possible stall as an upper bound on the number of
|
|
// times we should retry the pending queue because of a hazard.
|
|
unsigned MaxObservedStall;
|
|
#endif
|
|
|
|
public:
|
|
/// Pending queues extend the ready queues with the same ID and the
|
|
/// PendingFlag set.
|
|
SchedBoundary(unsigned ID, const Twine &Name):
|
|
DAG(nullptr), SchedModel(nullptr), Rem(nullptr), Available(ID, Name+".A"),
|
|
Pending(ID << LogMaxQID, Name+".P"),
|
|
HazardRec(nullptr) {
|
|
reset();
|
|
}
|
|
|
|
~SchedBoundary();
|
|
|
|
void reset();
|
|
|
|
void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
|
|
SchedRemainder *rem);
|
|
|
|
bool isTop() const {
|
|
return Available.getID() == TopQID;
|
|
}
|
|
|
|
/// Number of cycles to issue the instructions scheduled in this zone.
|
|
unsigned getCurrCycle() const { return CurrCycle; }
|
|
|
|
/// Micro-ops issued in the current cycle
|
|
unsigned getCurrMOps() const { return CurrMOps; }
|
|
|
|
/// Return true if the given SU is used by the most recently scheduled
|
|
/// instruction.
|
|
bool isNextSU(const SUnit *SU) const { return NextSUs.count(SU); }
|
|
|
|
// The latency of dependence chains leading into this zone.
|
|
unsigned getDependentLatency() const { return DependentLatency; }
|
|
|
|
/// Get the number of latency cycles "covered" by the scheduled
|
|
/// instructions. This is the larger of the critical path within the zone
|
|
/// and the number of cycles required to issue the instructions.
|
|
unsigned getScheduledLatency() const {
|
|
return std::max(ExpectedLatency, CurrCycle);
|
|
}
|
|
|
|
unsigned getUnscheduledLatency(SUnit *SU) const {
|
|
return isTop() ? SU->getHeight() : SU->getDepth();
|
|
}
|
|
|
|
unsigned getResourceCount(unsigned ResIdx) const {
|
|
return ExecutedResCounts[ResIdx];
|
|
}
|
|
|
|
/// Get the scaled count of scheduled micro-ops and resources, including
|
|
/// executed resources.
|
|
unsigned getCriticalCount() const {
|
|
if (!ZoneCritResIdx)
|
|
return RetiredMOps * SchedModel->getMicroOpFactor();
|
|
return getResourceCount(ZoneCritResIdx);
|
|
}
|
|
|
|
/// Get a scaled count for the minimum execution time of the scheduled
|
|
/// micro-ops that are ready to execute by getExecutedCount. Notice the
|
|
/// feedback loop.
|
|
unsigned getExecutedCount() const {
|
|
return std::max(CurrCycle * SchedModel->getLatencyFactor(),
|
|
MaxExecutedResCount);
|
|
}
|
|
|
|
unsigned getZoneCritResIdx() const { return ZoneCritResIdx; }
|
|
|
|
// Is the scheduled region resource limited vs. latency limited.
|
|
bool isResourceLimited() const { return IsResourceLimited; }
|
|
|
|
/// Get the difference between the given SUnit's ready time and the current
|
|
/// cycle.
|
|
unsigned getLatencyStallCycles(SUnit *SU);
|
|
|
|
unsigned getNextResourceCycle(unsigned PIdx, unsigned Cycles);
|
|
|
|
bool checkHazard(SUnit *SU);
|
|
|
|
unsigned findMaxLatency(ArrayRef<SUnit*> ReadySUs);
|
|
|
|
unsigned getOtherResourceCount(unsigned &OtherCritIdx);
|
|
|
|
void releaseNode(SUnit *SU, unsigned ReadyCycle);
|
|
|
|
void releaseTopNode(SUnit *SU);
|
|
|
|
void releaseBottomNode(SUnit *SU);
|
|
|
|
void bumpCycle(unsigned NextCycle);
|
|
|
|
void incExecutedResources(unsigned PIdx, unsigned Count);
|
|
|
|
unsigned countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle);
|
|
|
|
void bumpNode(SUnit *SU);
|
|
|
|
void releasePending();
|
|
|
|
void removeReady(SUnit *SU);
|
|
|
|
/// Call this before applying any other heuristics to the Available queue.
|
|
/// Updates the Available/Pending Q's if necessary and returns the single
|
|
/// available instruction, or NULL if there are multiple candidates.
|
|
SUnit *pickOnlyChoice();
|
|
|
|
#ifndef NDEBUG
|
|
void dumpScheduledState();
|
|
#endif
|
|
};
|
|
|
|
/// Base class for GenericScheduler. This class maintains information about
|
|
/// scheduling candidates based on TargetSchedModel making it easy to implement
|
|
/// heuristics for either preRA or postRA scheduling.
|
|
class GenericSchedulerBase : public MachineSchedStrategy {
|
|
public:
|
|
/// Represent the type of SchedCandidate found within a single queue.
|
|
/// pickNodeBidirectional depends on these listed by decreasing priority.
|
|
enum CandReason {
|
|
NoCand, PhysRegCopy, RegExcess, RegCritical, Stall, Cluster, Weak, RegMax,
|
|
ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
|
|
TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
|
|
|
|
#ifndef NDEBUG
|
|
static const char *getReasonStr(GenericSchedulerBase::CandReason Reason);
|
|
#endif
|
|
|
|
/// Policy for scheduling the next instruction in the candidate's zone.
|
|
struct CandPolicy {
|
|
bool ReduceLatency;
|
|
unsigned ReduceResIdx;
|
|
unsigned DemandResIdx;
|
|
|
|
CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {}
|
|
};
|
|
|
|
/// Status of an instruction's critical resource consumption.
|
|
struct SchedResourceDelta {
|
|
// Count critical resources in the scheduled region required by SU.
|
|
unsigned CritResources;
|
|
|
|
// Count critical resources from another region consumed by SU.
|
|
unsigned DemandedResources;
|
|
|
|
SchedResourceDelta(): CritResources(0), DemandedResources(0) {}
|
|
|
|
bool operator==(const SchedResourceDelta &RHS) const {
|
|
return CritResources == RHS.CritResources
|
|
&& DemandedResources == RHS.DemandedResources;
|
|
}
|
|
bool operator!=(const SchedResourceDelta &RHS) const {
|
|
return !operator==(RHS);
|
|
}
|
|
};
|
|
|
|
/// Store the state used by GenericScheduler heuristics, required for the
|
|
/// lifetime of one invocation of pickNode().
|
|
struct SchedCandidate {
|
|
CandPolicy Policy;
|
|
|
|
// The best SUnit candidate.
|
|
SUnit *SU;
|
|
|
|
// The reason for this candidate.
|
|
CandReason Reason;
|
|
|
|
// Set of reasons that apply to multiple candidates.
|
|
uint32_t RepeatReasonSet;
|
|
|
|
// Register pressure values for the best candidate.
|
|
RegPressureDelta RPDelta;
|
|
|
|
// Critical resource consumption of the best candidate.
|
|
SchedResourceDelta ResDelta;
|
|
|
|
SchedCandidate(const CandPolicy &policy)
|
|
: Policy(policy), SU(nullptr), Reason(NoCand), RepeatReasonSet(0) {}
|
|
|
|
bool isValid() const { return SU; }
|
|
|
|
// Copy the status of another candidate without changing policy.
|
|
void setBest(SchedCandidate &Best) {
|
|
assert(Best.Reason != NoCand && "uninitialized Sched candidate");
|
|
SU = Best.SU;
|
|
Reason = Best.Reason;
|
|
RPDelta = Best.RPDelta;
|
|
ResDelta = Best.ResDelta;
|
|
}
|
|
|
|
bool isRepeat(CandReason R) { return RepeatReasonSet & (1 << R); }
|
|
void setRepeat(CandReason R) { RepeatReasonSet |= (1 << R); }
|
|
|
|
void initResourceDelta(const ScheduleDAGMI *DAG,
|
|
const TargetSchedModel *SchedModel);
|
|
};
|
|
|
|
protected:
|
|
const MachineSchedContext *Context;
|
|
const TargetSchedModel *SchedModel;
|
|
const TargetRegisterInfo *TRI;
|
|
|
|
SchedRemainder Rem;
|
|
protected:
|
|
GenericSchedulerBase(const MachineSchedContext *C):
|
|
Context(C), SchedModel(nullptr), TRI(nullptr) {}
|
|
|
|
void setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone,
|
|
SchedBoundary *OtherZone);
|
|
|
|
#ifndef NDEBUG
|
|
void traceCandidate(const SchedCandidate &Cand);
|
|
#endif
|
|
};
|
|
|
|
/// GenericScheduler shrinks the unscheduled zone using heuristics to balance
|
|
/// the schedule.
|
|
class GenericScheduler : public GenericSchedulerBase {
|
|
ScheduleDAGMILive *DAG;
|
|
|
|
// State of the top and bottom scheduled instruction boundaries.
|
|
SchedBoundary Top;
|
|
SchedBoundary Bot;
|
|
|
|
MachineSchedPolicy RegionPolicy;
|
|
public:
|
|
GenericScheduler(const MachineSchedContext *C):
|
|
GenericSchedulerBase(C), DAG(nullptr), Top(SchedBoundary::TopQID, "TopQ"),
|
|
Bot(SchedBoundary::BotQID, "BotQ") {}
|
|
|
|
void initPolicy(MachineBasicBlock::iterator Begin,
|
|
MachineBasicBlock::iterator End,
|
|
unsigned NumRegionInstrs) override;
|
|
|
|
bool shouldTrackPressure() const override {
|
|
return RegionPolicy.ShouldTrackPressure;
|
|
}
|
|
|
|
void initialize(ScheduleDAGMI *dag) override;
|
|
|
|
SUnit *pickNode(bool &IsTopNode) override;
|
|
|
|
void schedNode(SUnit *SU, bool IsTopNode) override;
|
|
|
|
void releaseTopNode(SUnit *SU) override {
|
|
Top.releaseTopNode(SU);
|
|
}
|
|
|
|
void releaseBottomNode(SUnit *SU) override {
|
|
Bot.releaseBottomNode(SU);
|
|
}
|
|
|
|
void registerRoots() override;
|
|
|
|
protected:
|
|
void checkAcyclicLatency();
|
|
|
|
void tryCandidate(SchedCandidate &Cand,
|
|
SchedCandidate &TryCand,
|
|
SchedBoundary &Zone,
|
|
const RegPressureTracker &RPTracker,
|
|
RegPressureTracker &TempTracker);
|
|
|
|
SUnit *pickNodeBidirectional(bool &IsTopNode);
|
|
|
|
void pickNodeFromQueue(SchedBoundary &Zone,
|
|
const RegPressureTracker &RPTracker,
|
|
SchedCandidate &Candidate);
|
|
|
|
void reschedulePhysRegCopies(SUnit *SU, bool isTop);
|
|
};
|
|
|
|
/// PostGenericScheduler - Interface to the scheduling algorithm used by
|
|
/// ScheduleDAGMI.
|
|
///
|
|
/// Callbacks from ScheduleDAGMI:
|
|
/// initPolicy -> initialize(DAG) -> registerRoots -> pickNode ...
|
|
class PostGenericScheduler : public GenericSchedulerBase {
|
|
ScheduleDAGMI *DAG;
|
|
SchedBoundary Top;
|
|
SmallVector<SUnit*, 8> BotRoots;
|
|
public:
|
|
PostGenericScheduler(const MachineSchedContext *C):
|
|
GenericSchedulerBase(C), Top(SchedBoundary::TopQID, "TopQ") {}
|
|
|
|
virtual ~PostGenericScheduler() {}
|
|
|
|
void initPolicy(MachineBasicBlock::iterator Begin,
|
|
MachineBasicBlock::iterator End,
|
|
unsigned NumRegionInstrs) override {
|
|
/* no configurable policy */
|
|
};
|
|
|
|
/// PostRA scheduling does not track pressure.
|
|
bool shouldTrackPressure() const override { return false; }
|
|
|
|
void initialize(ScheduleDAGMI *Dag) override;
|
|
|
|
void registerRoots() override;
|
|
|
|
SUnit *pickNode(bool &IsTopNode) override;
|
|
|
|
void scheduleTree(unsigned SubtreeID) override {
|
|
llvm_unreachable("PostRA scheduler does not support subtree analysis.");
|
|
}
|
|
|
|
void schedNode(SUnit *SU, bool IsTopNode) override;
|
|
|
|
void releaseTopNode(SUnit *SU) override {
|
|
Top.releaseTopNode(SU);
|
|
}
|
|
|
|
// Only called for roots.
|
|
void releaseBottomNode(SUnit *SU) override {
|
|
BotRoots.push_back(SU);
|
|
}
|
|
|
|
protected:
|
|
void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand);
|
|
|
|
void pickNodeFromQueue(SchedCandidate &Cand);
|
|
};
|
|
|
|
} // namespace llvm
|
|
|
|
#endif
|