Chandler Carruth ce184e95f9 [x86] Add a ZERO_EXTEND_VECTOR_INREG DAG node and use it when widening ... vector types to be legal and a ZERO_EXTEND node is encountered. When we use widening to legalize vector types, extend nodes are a real challenge. Either the input or output is likely to be legal, but in many cases not both. As a consequence, we don't really have any way to represent this situation and the prior code in the widening legalization framework would just scalarize the extend operation completely. This patch introduces a new DAG node to represent doing a zero extend of a vector "in register". The core of the idea is to allow legal but different vector types in the input and output. The output vector must have fewer lanes but wider elements. The operation is defined to zero extend the low elements of the input to the size of the output elements, and drop all of the high elements which don't have a corresponding lane in the output vector. It also includes generic expansion of this node in terms of blending a zero vector into the high elements of the vector and bitcasting across. This in turn yields extremely nice code for x86 SSE2 when we use the new widening legalization logic in conjunction with the new shuffle lowering logic. There is still more to do here. We need to support sign extension, any extension, and potentially int-to-float conversions. My current plan is to continue using similar synthetic nodes to model each of these transitions with generic lowering code for each one. However, with this patch LLVM already reaches performance parity with GCC for the core C loops of the x264 code (assuming you disable the hand-written assembly versions) when compiling for SSE2 and SSE3 architectures and enabling the new widening and lowering logic for vectors. Differential Revision: http://reviews.llvm.org/D4405 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212610 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-09 10:58:18 +00:00
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Analysis	Improve BasicAA CS-CS queries	2014-07-08 23:16:49 +00:00
AsmParser
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CodeGen	[x86] Add a ZERO_EXTEND_VECTOR_INREG DAG node and use it when widening	2014-07-09 10:58:18 +00:00
DebugInfo
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MC	Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it.	2014-07-08 08:59:22 +00:00
Object	Add support for BSD format Archive map symbols (aka the table of contents	2014-07-08 22:10:02 +00:00
Option
ProfileData
Support	SourceMgr: consistently use 'unsigned' for the memory buffer ID type	2014-07-09 08:30:15 +00:00
TableGen
Target	[x86] Add a ZERO_EXTEND_VECTOR_INREG DAG node and use it when widening	2014-07-09 10:58:18 +00:00
Transforms	[ASan/Win] Don't instrument COMDAT globals. Properly fixes PR20244.	2014-07-09 08:35:33 +00:00
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