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Summary: Offset of frame index is calculated by NVPTXPrologEpilogPass. Before that the correct offset of stack objects cannot be obtained, which leads to wrong offset if there are more than 2 frame objects. This patch move NVPTXPeephole after NVPTXPrologEpilogPass. Because the frame index is already replaced by %VRFrame in NVPTXPrologEpilogPass, we check VRFrame register instead, and try to remove the VRFrame if there is no usage after NVPTXPeephole pass. Patched by Xuetian Weng. Test Plan: Strengthened test/CodeGen/NVPTX/local-stack-frame.ll to check the offset calculation based on SP and SPL. Reviewers: jholewinski, jingyue Reviewed By: jingyue Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10853 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241185 91177308-0d34-0410-b5e6-96231b3b80d8
155 lines
4.9 KiB
C++
155 lines
4.9 KiB
C++
//===-- NVPTXPeephole.cpp - NVPTX Peephole Optimiztions -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// In NVPTX, NVPTXFrameLowering will emit following instruction at the beginning
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// of a MachineFunction.
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//
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// mov %SPL, %depot
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// cvta.local %SP, %SPL
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//
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// Because Frame Index is a generic address and alloca can only return generic
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// pointer, without this pass the instructions producing alloca'ed address will
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// be based on %SP. NVPTXLowerAlloca tends to help replace store and load on
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// this address with their .local versions, but this may introduce a lot of
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// cvta.to.local instructions. Performance can be improved if we avoid casting
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// address back and forth and directly calculate local address based on %SPL.
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// This peephole pass optimizes these cases, for example
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//
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// It will transform the following pattern
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// %vreg0<def> = LEA_ADDRi64 %VRFrame, 4
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// %vreg1<def> = cvta_to_local_yes_64 %vreg0
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//
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// into
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// %vreg1<def> = LEA_ADDRi64 %VRFrameLocal, 4
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//
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// %VRFrameLocal is the virtual register name of %SPL
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTX.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "nvptx-peephole"
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namespace llvm {
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void initializeNVPTXPeepholePass(PassRegistry &);
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}
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namespace {
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struct NVPTXPeephole : public MachineFunctionPass {
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public:
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static char ID;
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NVPTXPeephole() : MachineFunctionPass(ID) {
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initializeNVPTXPeepholePass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "NVPTX optimize redundant cvta.to.local instruction";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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}
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char NVPTXPeephole::ID = 0;
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INITIALIZE_PASS(NVPTXPeephole, "nvptx-peephole", "NVPTX Peephole", false, false)
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static bool isCVTAToLocalCombinationCandidate(MachineInstr &Root) {
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auto &MBB = *Root.getParent();
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auto &MF = *MBB.getParent();
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// Check current instruction is cvta.to.local
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if (Root.getOpcode() != NVPTX::cvta_to_local_yes_64 &&
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Root.getOpcode() != NVPTX::cvta_to_local_yes)
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return false;
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auto &Op = Root.getOperand(1);
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const auto &MRI = MF.getRegInfo();
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MachineInstr *GenericAddrDef = nullptr;
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if (Op.isReg() && TargetRegisterInfo::isVirtualRegister(Op.getReg())) {
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GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg());
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}
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// Check the register operand is uniquely defined by LEA_ADDRi instruction
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if (!GenericAddrDef || GenericAddrDef->getParent() != &MBB ||
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(GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi64 &&
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GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi)) {
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return false;
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}
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// Check the LEA_ADDRi operand is Frame index
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auto &BaseAddrOp = GenericAddrDef->getOperand(1);
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if (BaseAddrOp.isReg() && BaseAddrOp.getReg() == NVPTX::VRFrame) {
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return true;
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}
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return false;
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}
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static void CombineCVTAToLocal(MachineInstr &Root) {
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auto &MBB = *Root.getParent();
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auto &MF = *MBB.getParent();
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const auto &MRI = MF.getRegInfo();
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
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MachineInstrBuilder MIB =
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BuildMI(MF, Root.getDebugLoc(), TII->get(Prev.getOpcode()),
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Root.getOperand(0).getReg())
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.addReg(NVPTX::VRFrameLocal)
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.addOperand(Prev.getOperand(2));
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MBB.insert((MachineBasicBlock::iterator)&Root, MIB);
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// Check if MRI has only one non dbg use, which is Root
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if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) {
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Prev.eraseFromParentAndMarkDBGValuesForRemoval();
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}
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Root.eraseFromParentAndMarkDBGValuesForRemoval();
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}
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bool NVPTXPeephole::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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// Loop over all of the basic blocks.
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for (auto &MBB : MF) {
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// Traverse the basic block.
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auto BlockIter = MBB.begin();
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while (BlockIter != MBB.end()) {
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auto &MI = *BlockIter++;
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if (isCVTAToLocalCombinationCandidate(MI)) {
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CombineCVTAToLocal(MI);
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Changed = true;
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}
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} // Instruction
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} // Basic Block
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// Remove unnecessary %VRFrame = cvta.local %VRFrameLocal
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const auto &MRI = MF.getRegInfo();
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if (MRI.use_empty(NVPTX::VRFrame)) {
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if (auto MI = MRI.getUniqueVRegDef(NVPTX::VRFrame)) {
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MI->eraseFromParentAndMarkDBGValuesForRemoval();
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}
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}
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return Changed;
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}
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MachineFunctionPass *llvm::createNVPTXPeephole() { return new NVPTXPeephole(); }
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