mirror of
https://github.com/c64scene-ar/llvm-6502.git
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49683f3c96
The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
1295 lines
49 KiB
C++
1295 lines
49 KiB
C++
//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that NVPTX uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTX.h"
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#include "NVPTXISelLowering.h"
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#include "NVPTXTargetMachine.h"
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#include "NVPTXTargetObjectFile.h"
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#include "NVPTXUtilities.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/IntrinsicInst.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Module.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CallSite.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/MC/MCSectionELF.h"
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#include <sstream>
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#undef DEBUG_TYPE
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#define DEBUG_TYPE "nvptx-lower"
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using namespace llvm;
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static unsigned int uniqueCallSite = 0;
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static cl::opt<bool>
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RetainVectorOperands("nvptx-codegen-vectors",
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cl::desc("NVPTX Specific: Retain LLVM's vectors and generate PTX vectors"),
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cl::init(true));
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static cl::opt<bool>
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sched4reg("nvptx-sched4reg",
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cl::desc("NVPTX Specific: schedule for register pressue"),
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cl::init(false));
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// NVPTXTargetLowering Constructor.
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NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM)
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: TargetLowering(TM, new NVPTXTargetObjectFile()),
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nvTM(&TM),
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nvptxSubtarget(TM.getSubtarget<NVPTXSubtarget>()) {
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// always lower memset, memcpy, and memmove intrinsics to load/store
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// instructions, rather
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// then generating calls to memset, mempcy or memmove.
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maxStoresPerMemset = (unsigned)0xFFFFFFFF;
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maxStoresPerMemcpy = (unsigned)0xFFFFFFFF;
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maxStoresPerMemmove = (unsigned)0xFFFFFFFF;
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setBooleanContents(ZeroOrNegativeOneBooleanContent);
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// Jump is Expensive. Don't create extra control flow for 'and', 'or'
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// condition branches.
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setJumpIsExpensive(true);
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// By default, use the Source scheduling
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if (sched4reg)
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setSchedulingPreference(Sched::RegPressure);
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else
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setSchedulingPreference(Sched::Source);
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addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
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addRegisterClass(MVT::i8, &NVPTX::Int8RegsRegClass);
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addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
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addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
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addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
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addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
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addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
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if (RetainVectorOperands) {
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addRegisterClass(MVT::v2f32, &NVPTX::V2F32RegsRegClass);
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addRegisterClass(MVT::v4f32, &NVPTX::V4F32RegsRegClass);
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addRegisterClass(MVT::v2i32, &NVPTX::V2I32RegsRegClass);
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addRegisterClass(MVT::v4i32, &NVPTX::V4I32RegsRegClass);
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addRegisterClass(MVT::v2f64, &NVPTX::V2F64RegsRegClass);
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addRegisterClass(MVT::v2i64, &NVPTX::V2I64RegsRegClass);
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addRegisterClass(MVT::v2i16, &NVPTX::V2I16RegsRegClass);
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addRegisterClass(MVT::v4i16, &NVPTX::V4I16RegsRegClass);
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addRegisterClass(MVT::v2i8, &NVPTX::V2I8RegsRegClass);
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addRegisterClass(MVT::v4i8, &NVPTX::V4I8RegsRegClass);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32 , Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32 , Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16 , Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i8 , Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64 , Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64 , Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32 , Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32 , Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16 , Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i8 , Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32 , Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32 , Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i16 , Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i8 , Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i64 , Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f64 , Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32 , Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32 , Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i16 , Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i8 , Custom);
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}
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// Operations not directly supported by NVPTX.
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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if (nvptxSubtarget.hasROT64()) {
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setOperationAction(ISD::ROTL , MVT::i64, Legal);
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setOperationAction(ISD::ROTR , MVT::i64, Legal);
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}
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else {
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setOperationAction(ISD::ROTL , MVT::i64, Expand);
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setOperationAction(ISD::ROTR , MVT::i64, Expand);
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}
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if (nvptxSubtarget.hasROT32()) {
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setOperationAction(ISD::ROTL , MVT::i32, Legal);
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setOperationAction(ISD::ROTR , MVT::i32, Legal);
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}
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else {
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setOperationAction(ISD::ROTL , MVT::i32, Expand);
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setOperationAction(ISD::ROTR , MVT::i32, Expand);
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}
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setOperationAction(ISD::ROTL , MVT::i16, Expand);
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setOperationAction(ISD::ROTR , MVT::i16, Expand);
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setOperationAction(ISD::ROTL , MVT::i8, Expand);
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setOperationAction(ISD::ROTR , MVT::i8, Expand);
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setOperationAction(ISD::BSWAP , MVT::i16, Expand);
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setOperationAction(ISD::BSWAP , MVT::i32, Expand);
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setOperationAction(ISD::BSWAP , MVT::i64, Expand);
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// Indirect branch is not supported.
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// This also disables Jump Table creation.
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BRIND, MVT::Other, Expand);
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setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
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setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
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// We want to legalize constant related memmove and memcopy
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// intrinsics.
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
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// Turn FP extload into load/fextend
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
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// Turn FP truncstore into trunc + store.
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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// PTX does not support load / store predicate registers
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setOperationAction(ISD::LOAD, MVT::i1, Expand);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::STORE, MVT::i1, Expand);
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setTruncStoreAction(MVT::i64, MVT::i1, Expand);
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setTruncStoreAction(MVT::i32, MVT::i1, Expand);
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setTruncStoreAction(MVT::i16, MVT::i1, Expand);
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setTruncStoreAction(MVT::i8, MVT::i1, Expand);
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// This is legal in NVPTX
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setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
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setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
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// TRAP can be lowered to PTX trap
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setOperationAction(ISD::TRAP, MVT::Other, Legal);
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// By default, CONCAT_VECTORS is implemented via store/load
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// through stack. It is slow and uses local memory. We need
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// to custom-lowering them.
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32 , Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32 , Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i16 , Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i8 , Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64 , Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64 , Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i32 , Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f32 , Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i16 , Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i8 , Custom);
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// Expand vector int to float and float to int conversions
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// - For SINT_TO_FP and UINT_TO_FP, the src type
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// (Node->getOperand(0).getValueType())
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// is used to determine the action, while for FP_TO_UINT and FP_TO_SINT,
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// the dest type (Node->getValueType(0)) is used.
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//
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// See VectorLegalizer::LegalizeOp() (LegalizeVectorOps.cpp) for the vector
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// case, and
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// SelectionDAGLegalize::LegalizeOp() (LegalizeDAG.cpp) for the scalar case.
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//
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// That is why v4i32 or v2i32 are used here.
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//
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// The expansion for vectors happens in VectorLegalizer::LegalizeOp()
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// (LegalizeVectorOps.cpp).
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
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setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Expand);
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setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Expand);
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setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
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// Now deduce the information based on the above mentioned
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// actions
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computeRegisterProperties();
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}
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const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case NVPTXISD::CALL: return "NVPTXISD::CALL";
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case NVPTXISD::RET_FLAG: return "NVPTXISD::RET_FLAG";
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case NVPTXISD::Wrapper: return "NVPTXISD::Wrapper";
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case NVPTXISD::NVBuiltin: return "NVPTXISD::NVBuiltin";
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case NVPTXISD::DeclareParam: return "NVPTXISD::DeclareParam";
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case NVPTXISD::DeclareScalarParam:
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return "NVPTXISD::DeclareScalarParam";
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case NVPTXISD::DeclareRet: return "NVPTXISD::DeclareRet";
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case NVPTXISD::DeclareRetParam: return "NVPTXISD::DeclareRetParam";
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case NVPTXISD::PrintCall: return "NVPTXISD::PrintCall";
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case NVPTXISD::LoadParam: return "NVPTXISD::LoadParam";
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case NVPTXISD::StoreParam: return "NVPTXISD::StoreParam";
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case NVPTXISD::StoreParamS32: return "NVPTXISD::StoreParamS32";
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case NVPTXISD::StoreParamU32: return "NVPTXISD::StoreParamU32";
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case NVPTXISD::MoveToParam: return "NVPTXISD::MoveToParam";
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case NVPTXISD::CallArgBegin: return "NVPTXISD::CallArgBegin";
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case NVPTXISD::CallArg: return "NVPTXISD::CallArg";
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case NVPTXISD::LastCallArg: return "NVPTXISD::LastCallArg";
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case NVPTXISD::CallArgEnd: return "NVPTXISD::CallArgEnd";
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case NVPTXISD::CallVoid: return "NVPTXISD::CallVoid";
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case NVPTXISD::CallVal: return "NVPTXISD::CallVal";
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case NVPTXISD::CallSymbol: return "NVPTXISD::CallSymbol";
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case NVPTXISD::Prototype: return "NVPTXISD::Prototype";
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case NVPTXISD::MoveParam: return "NVPTXISD::MoveParam";
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case NVPTXISD::MoveRetval: return "NVPTXISD::MoveRetval";
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case NVPTXISD::MoveToRetval: return "NVPTXISD::MoveToRetval";
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case NVPTXISD::StoreRetval: return "NVPTXISD::StoreRetval";
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case NVPTXISD::PseudoUseParam: return "NVPTXISD::PseudoUseParam";
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case NVPTXISD::RETURN: return "NVPTXISD::RETURN";
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case NVPTXISD::CallSeqBegin: return "NVPTXISD::CallSeqBegin";
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case NVPTXISD::CallSeqEnd: return "NVPTXISD::CallSeqEnd";
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}
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}
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SDValue
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NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
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DebugLoc dl = Op.getDebugLoc();
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const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
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return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
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}
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std::string NVPTXTargetLowering::getPrototype(Type *retTy,
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const ArgListTy &Args,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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unsigned retAlignment) const {
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bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
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std::stringstream O;
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O << "prototype_" << uniqueCallSite << " : .callprototype ";
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if (retTy->getTypeID() == Type::VoidTyID)
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O << "()";
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else {
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O << "(";
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if (isABI) {
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if (retTy->isPrimitiveType() || retTy->isIntegerTy()) {
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unsigned size = 0;
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if (const IntegerType *ITy = dyn_cast<IntegerType>(retTy)) {
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size = ITy->getBitWidth();
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if (size < 32) size = 32;
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}
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else {
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assert(retTy->isFloatingPointTy() &&
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"Floating point type expected here");
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size = retTy->getPrimitiveSizeInBits();
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}
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O << ".param .b" << size << " _";
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}
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else if (isa<PointerType>(retTy))
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O << ".param .b" << getPointerTy().getSizeInBits()
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<< " _";
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else {
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if ((retTy->getTypeID() == Type::StructTyID) ||
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isa<VectorType>(retTy)) {
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SmallVector<EVT, 16> vtparts;
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ComputeValueVTs(*this, retTy, vtparts);
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unsigned totalsz = 0;
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for (unsigned i=0,e=vtparts.size(); i!=e; ++i) {
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unsigned elems = 1;
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EVT elemtype = vtparts[i];
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if (vtparts[i].isVector()) {
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elems = vtparts[i].getVectorNumElements();
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elemtype = vtparts[i].getVectorElementType();
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}
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for (unsigned j=0, je=elems; j!=je; ++j) {
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unsigned sz = elemtype.getSizeInBits();
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if (elemtype.isInteger() && (sz < 8)) sz = 8;
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totalsz += sz/8;
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}
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}
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O << ".param .align "
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<< retAlignment
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<< " .b8 _["
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<< totalsz << "]";
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}
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else {
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assert(false &&
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"Unknown return type");
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}
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}
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}
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else {
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SmallVector<EVT, 16> vtparts;
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ComputeValueVTs(*this, retTy, vtparts);
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unsigned idx = 0;
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for (unsigned i=0,e=vtparts.size(); i!=e; ++i) {
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unsigned elems = 1;
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EVT elemtype = vtparts[i];
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if (vtparts[i].isVector()) {
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elems = vtparts[i].getVectorNumElements();
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elemtype = vtparts[i].getVectorElementType();
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}
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for (unsigned j=0, je=elems; j!=je; ++j) {
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unsigned sz = elemtype.getSizeInBits();
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if (elemtype.isInteger() && (sz < 32)) sz = 32;
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O << ".reg .b" << sz << " _";
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if (j<je-1) O << ", ";
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++idx;
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}
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if (i < e-1)
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O << ", ";
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}
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}
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O << ") ";
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}
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O << "_ (";
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bool first = true;
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MVT thePointerTy = getPointerTy();
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for (unsigned i=0,e=Args.size(); i!=e; ++i) {
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const Type *Ty = Args[i].Ty;
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if (!first) {
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O << ", ";
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}
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first = false;
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if (Outs[i].Flags.isByVal() == false) {
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unsigned sz = 0;
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if (isa<IntegerType>(Ty)) {
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sz = cast<IntegerType>(Ty)->getBitWidth();
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if (sz < 32) sz = 32;
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}
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else if (isa<PointerType>(Ty))
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sz = thePointerTy.getSizeInBits();
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else
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sz = Ty->getPrimitiveSizeInBits();
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if (isABI)
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O << ".param .b" << sz << " ";
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else
|
|
O << ".reg .b" << sz << " ";
|
|
O << "_";
|
|
continue;
|
|
}
|
|
const PointerType *PTy = dyn_cast<PointerType>(Ty);
|
|
assert(PTy &&
|
|
"Param with byval attribute should be a pointer type");
|
|
Type *ETy = PTy->getElementType();
|
|
|
|
if (isABI) {
|
|
unsigned align = Outs[i].Flags.getByValAlign();
|
|
unsigned sz = getTargetData()->getTypeAllocSize(ETy);
|
|
O << ".param .align " << align
|
|
<< " .b8 ";
|
|
O << "_";
|
|
O << "[" << sz << "]";
|
|
continue;
|
|
}
|
|
else {
|
|
SmallVector<EVT, 16> vtparts;
|
|
ComputeValueVTs(*this, ETy, vtparts);
|
|
for (unsigned i=0,e=vtparts.size(); i!=e; ++i) {
|
|
unsigned elems = 1;
|
|
EVT elemtype = vtparts[i];
|
|
if (vtparts[i].isVector()) {
|
|
elems = vtparts[i].getVectorNumElements();
|
|
elemtype = vtparts[i].getVectorElementType();
|
|
}
|
|
|
|
for (unsigned j=0,je=elems; j!=je; ++j) {
|
|
unsigned sz = elemtype.getSizeInBits();
|
|
if (elemtype.isInteger() && (sz < 32)) sz = 32;
|
|
O << ".reg .b" << sz << " ";
|
|
O << "_";
|
|
if (j<je-1) O << ", ";
|
|
}
|
|
if (i<e-1)
|
|
O << ", ";
|
|
}
|
|
continue;
|
|
}
|
|
}
|
|
O << ");";
|
|
return O.str();
|
|
}
|
|
|
|
|
|
#if 0
|
|
SDValue
|
|
NVPTXTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
bool doesNotRet, bool &isTailCall,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals, Type *retTy,
|
|
const ArgListTy &Args) const {
|
|
bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
|
|
|
|
SDValue tempChain = Chain;
|
|
Chain = DAG.getCALLSEQ_START(Chain,
|
|
DAG.getIntPtrConstant(uniqueCallSite, true));
|
|
SDValue InFlag = Chain.getValue(1);
|
|
|
|
assert((Outs.size() == Args.size()) &&
|
|
"Unexpected number of arguments to function call");
|
|
unsigned paramCount = 0;
|
|
// Declare the .params or .reg need to pass values
|
|
// to the function
|
|
for (unsigned i=0, e=Outs.size(); i!=e; ++i) {
|
|
EVT VT = Outs[i].VT;
|
|
|
|
if (Outs[i].Flags.isByVal() == false) {
|
|
// Plain scalar
|
|
// for ABI, declare .param .b<size> .param<n>;
|
|
// for nonABI, declare .reg .b<size> .param<n>;
|
|
unsigned isReg = 1;
|
|
if (isABI)
|
|
isReg = 0;
|
|
unsigned sz = VT.getSizeInBits();
|
|
if (VT.isInteger() && (sz < 32)) sz = 32;
|
|
SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue DeclareParamOps[] = { Chain,
|
|
DAG.getConstant(paramCount, MVT::i32),
|
|
DAG.getConstant(sz, MVT::i32),
|
|
DAG.getConstant(isReg, MVT::i32),
|
|
InFlag };
|
|
Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
|
|
DeclareParamOps, 5);
|
|
InFlag = Chain.getValue(1);
|
|
SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
|
|
DAG.getConstant(0, MVT::i32), OutVals[i], InFlag };
|
|
|
|
unsigned opcode = NVPTXISD::StoreParam;
|
|
if (isReg)
|
|
opcode = NVPTXISD::MoveToParam;
|
|
else {
|
|
if (Outs[i].Flags.isZExt())
|
|
opcode = NVPTXISD::StoreParamU32;
|
|
else if (Outs[i].Flags.isSExt())
|
|
opcode = NVPTXISD::StoreParamS32;
|
|
}
|
|
Chain = DAG.getNode(opcode, dl, CopyParamVTs, CopyParamOps, 5);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
++paramCount;
|
|
continue;
|
|
}
|
|
// struct or vector
|
|
SmallVector<EVT, 16> vtparts;
|
|
const PointerType *PTy = dyn_cast<PointerType>(Args[i].Ty);
|
|
assert(PTy &&
|
|
"Type of a byval parameter should be pointer");
|
|
ComputeValueVTs(*this, PTy->getElementType(), vtparts);
|
|
|
|
if (isABI) {
|
|
// declare .param .align 16 .b8 .param<n>[<size>];
|
|
unsigned sz = Outs[i].Flags.getByValSize();
|
|
SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
// The ByValAlign in the Outs[i].Flags is alway set at this point, so we
|
|
// don't need to
|
|
// worry about natural alignment or not. See TargetLowering::LowerCallTo()
|
|
SDValue DeclareParamOps[] = { Chain,
|
|
DAG.getConstant(Outs[i].Flags.getByValAlign(), MVT::i32),
|
|
DAG.getConstant(paramCount, MVT::i32),
|
|
DAG.getConstant(sz, MVT::i32),
|
|
InFlag };
|
|
Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
|
|
DeclareParamOps, 5);
|
|
InFlag = Chain.getValue(1);
|
|
unsigned curOffset = 0;
|
|
for (unsigned j=0,je=vtparts.size(); j!=je; ++j) {
|
|
unsigned elems = 1;
|
|
EVT elemtype = vtparts[j];
|
|
if (vtparts[j].isVector()) {
|
|
elems = vtparts[j].getVectorNumElements();
|
|
elemtype = vtparts[j].getVectorElementType();
|
|
}
|
|
for (unsigned k=0,ke=elems; k!=ke; ++k) {
|
|
unsigned sz = elemtype.getSizeInBits();
|
|
if (elemtype.isInteger() && (sz < 8)) sz = 8;
|
|
SDValue srcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
|
|
OutVals[i],
|
|
DAG.getConstant(curOffset,
|
|
getPointerTy()));
|
|
SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
|
|
MachinePointerInfo(), false, false, false, 0);
|
|
SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount,
|
|
MVT::i32),
|
|
DAG.getConstant(curOffset, MVT::i32),
|
|
theVal, InFlag };
|
|
Chain = DAG.getNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
|
|
CopyParamOps, 5);
|
|
InFlag = Chain.getValue(1);
|
|
curOffset += sz/8;
|
|
}
|
|
}
|
|
++paramCount;
|
|
continue;
|
|
}
|
|
// Non-abi, struct or vector
|
|
// Declare a bunch or .reg .b<size> .param<n>
|
|
unsigned curOffset = 0;
|
|
for (unsigned j=0,je=vtparts.size(); j!=je; ++j) {
|
|
unsigned elems = 1;
|
|
EVT elemtype = vtparts[j];
|
|
if (vtparts[j].isVector()) {
|
|
elems = vtparts[j].getVectorNumElements();
|
|
elemtype = vtparts[j].getVectorElementType();
|
|
}
|
|
for (unsigned k=0,ke=elems; k!=ke; ++k) {
|
|
unsigned sz = elemtype.getSizeInBits();
|
|
if (elemtype.isInteger() && (sz < 32)) sz = 32;
|
|
SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue DeclareParamOps[] = { Chain, DAG.getConstant(paramCount,
|
|
MVT::i32),
|
|
DAG.getConstant(sz, MVT::i32),
|
|
DAG.getConstant(1, MVT::i32),
|
|
InFlag };
|
|
Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
|
|
DeclareParamOps, 5);
|
|
InFlag = Chain.getValue(1);
|
|
SDValue srcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[i],
|
|
DAG.getConstant(curOffset,
|
|
getPointerTy()));
|
|
SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
|
|
MachinePointerInfo(), false, false, false, 0);
|
|
SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
|
|
DAG.getConstant(0, MVT::i32), theVal,
|
|
InFlag };
|
|
Chain = DAG.getNode(NVPTXISD::MoveToParam, dl, CopyParamVTs,
|
|
CopyParamOps, 5);
|
|
InFlag = Chain.getValue(1);
|
|
++paramCount;
|
|
}
|
|
}
|
|
}
|
|
|
|
GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
|
|
unsigned retAlignment = 0;
|
|
|
|
// Handle Result
|
|
unsigned retCount = 0;
|
|
if (Ins.size() > 0) {
|
|
SmallVector<EVT, 16> resvtparts;
|
|
ComputeValueVTs(*this, retTy, resvtparts);
|
|
|
|
// Declare one .param .align 16 .b8 func_retval0[<size>] for ABI or
|
|
// individual .reg .b<size> func_retval<0..> for non ABI
|
|
unsigned resultsz = 0;
|
|
for (unsigned i=0,e=resvtparts.size(); i!=e; ++i) {
|
|
unsigned elems = 1;
|
|
EVT elemtype = resvtparts[i];
|
|
if (resvtparts[i].isVector()) {
|
|
elems = resvtparts[i].getVectorNumElements();
|
|
elemtype = resvtparts[i].getVectorElementType();
|
|
}
|
|
for (unsigned j=0,je=elems; j!=je; ++j) {
|
|
unsigned sz = elemtype.getSizeInBits();
|
|
if (isABI == false) {
|
|
if (elemtype.isInteger() && (sz < 32)) sz = 32;
|
|
}
|
|
else {
|
|
if (elemtype.isInteger() && (sz < 8)) sz = 8;
|
|
}
|
|
if (isABI == false) {
|
|
SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue DeclareRetOps[] = { Chain, DAG.getConstant(2, MVT::i32),
|
|
DAG.getConstant(sz, MVT::i32),
|
|
DAG.getConstant(retCount, MVT::i32),
|
|
InFlag };
|
|
Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
|
|
DeclareRetOps, 5);
|
|
InFlag = Chain.getValue(1);
|
|
++retCount;
|
|
}
|
|
resultsz += sz;
|
|
}
|
|
}
|
|
if (isABI) {
|
|
if (retTy->isPrimitiveType() || retTy->isIntegerTy() ||
|
|
retTy->isPointerTy() ) {
|
|
// Scalar needs to be at least 32bit wide
|
|
if (resultsz < 32)
|
|
resultsz = 32;
|
|
SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, MVT::i32),
|
|
DAG.getConstant(resultsz, MVT::i32),
|
|
DAG.getConstant(0, MVT::i32), InFlag };
|
|
Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
|
|
DeclareRetOps, 5);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
else {
|
|
// @TODO: Re-enable getAlign calls. We do not have the
|
|
// ImmutableCallSite object here anymore.
|
|
//if (Func) { // direct call
|
|
//if (!llvm::getAlign(*(CS->getCalledFunction()), 0, retAlignment))
|
|
//retAlignment = TD->getABITypeAlignment(retTy);
|
|
//}
|
|
//else { // indirect call
|
|
//const CallInst *CallI = dyn_cast<CallInst>(CS->getInstruction());
|
|
//if (!llvm::getAlign(*CallI, 0, retAlignment))
|
|
//retAlignment = TD->getABITypeAlignment(retTy);
|
|
//}
|
|
// @TODO: Remove this hack!
|
|
// Functions with explicit alignment metadata will be broken, for now.
|
|
retAlignment = 16;
|
|
SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue DeclareRetOps[] = { Chain, DAG.getConstant(retAlignment,
|
|
MVT::i32),
|
|
DAG.getConstant(resultsz/8, MVT::i32),
|
|
DAG.getConstant(0, MVT::i32), InFlag };
|
|
Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
|
|
DeclareRetOps, 5);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!Func) {
|
|
// This is indirect function call case : PTX requires a prototype of the
|
|
// form
|
|
// proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
|
|
// to be emitted, and the label has to used as the last arg of call
|
|
// instruction.
|
|
// The prototype is embedded in a string and put as the operand for an
|
|
// INLINEASM SDNode.
|
|
SDVTList InlineAsmVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
std::string proto_string = getPrototype(retTy, Args, Outs, retAlignment);
|
|
const char *asmstr = nvTM->getManagedStrPool()->
|
|
getManagedString(proto_string.c_str())->c_str();
|
|
SDValue InlineAsmOps[] = { Chain,
|
|
DAG.getTargetExternalSymbol(asmstr,
|
|
getPointerTy()),
|
|
DAG.getMDNode(0),
|
|
DAG.getTargetConstant(0, MVT::i32), InFlag };
|
|
Chain = DAG.getNode(ISD::INLINEASM, dl, InlineAsmVTs, InlineAsmOps, 5);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
// Op to just print "call"
|
|
SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue PrintCallOps[] = { Chain,
|
|
DAG.getConstant(isABI ? ((Ins.size()==0) ? 0 : 1)
|
|
: retCount, MVT::i32),
|
|
InFlag };
|
|
Chain = DAG.getNode(Func?(NVPTXISD::PrintCallUni):(NVPTXISD::PrintCall), dl,
|
|
PrintCallVTs, PrintCallOps, 3);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// Ops to print out the function name
|
|
SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue CallVoidOps[] = { Chain, Callee, InFlag };
|
|
Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps, 3);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// Ops to print out the param list
|
|
SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue CallArgBeginOps[] = { Chain, InFlag };
|
|
Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
|
|
CallArgBeginOps, 2);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
for (unsigned i=0, e=paramCount; i!=e; ++i) {
|
|
unsigned opcode;
|
|
if (i==(e-1))
|
|
opcode = NVPTXISD::LastCallArg;
|
|
else
|
|
opcode = NVPTXISD::CallArg;
|
|
SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue CallArgOps[] = { Chain, DAG.getConstant(1, MVT::i32),
|
|
DAG.getConstant(i, MVT::i32),
|
|
InFlag };
|
|
Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps, 4);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue CallArgEndOps[] = { Chain,
|
|
DAG.getConstant(Func ? 1 : 0, MVT::i32),
|
|
InFlag };
|
|
Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps,
|
|
3);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
if (!Func) {
|
|
SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SDValue PrototypeOps[] = { Chain,
|
|
DAG.getConstant(uniqueCallSite, MVT::i32),
|
|
InFlag };
|
|
Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps, 3);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
|
|
// Generate loads from param memory/moves from registers for result
|
|
if (Ins.size() > 0) {
|
|
if (isABI) {
|
|
unsigned resoffset = 0;
|
|
for (unsigned i=0,e=Ins.size(); i!=e; ++i) {
|
|
unsigned sz = Ins[i].VT.getSizeInBits();
|
|
if (Ins[i].VT.isInteger() && (sz < 8)) sz = 8;
|
|
std::vector<EVT> LoadRetVTs;
|
|
LoadRetVTs.push_back(Ins[i].VT);
|
|
LoadRetVTs.push_back(MVT::Other); LoadRetVTs.push_back(MVT::Glue);
|
|
std::vector<SDValue> LoadRetOps;
|
|
LoadRetOps.push_back(Chain);
|
|
LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
|
|
LoadRetOps.push_back(DAG.getConstant(resoffset, MVT::i32));
|
|
LoadRetOps.push_back(InFlag);
|
|
SDValue retval = DAG.getNode(NVPTXISD::LoadParam, dl, LoadRetVTs,
|
|
&LoadRetOps[0], LoadRetOps.size());
|
|
Chain = retval.getValue(1);
|
|
InFlag = retval.getValue(2);
|
|
InVals.push_back(retval);
|
|
resoffset += sz/8;
|
|
}
|
|
}
|
|
else {
|
|
SmallVector<EVT, 16> resvtparts;
|
|
ComputeValueVTs(*this, retTy, resvtparts);
|
|
|
|
assert(Ins.size() == resvtparts.size() &&
|
|
"Unexpected number of return values in non-ABI case");
|
|
unsigned paramNum = 0;
|
|
for (unsigned i=0,e=Ins.size(); i!=e; ++i) {
|
|
assert(EVT(Ins[i].VT) == resvtparts[i] &&
|
|
"Unexpected EVT type in non-ABI case");
|
|
unsigned numelems = 1;
|
|
EVT elemtype = Ins[i].VT;
|
|
if (Ins[i].VT.isVector()) {
|
|
numelems = Ins[i].VT.getVectorNumElements();
|
|
elemtype = Ins[i].VT.getVectorElementType();
|
|
}
|
|
std::vector<SDValue> tempRetVals;
|
|
for (unsigned j=0; j<numelems; ++j) {
|
|
std::vector<EVT> MoveRetVTs;
|
|
MoveRetVTs.push_back(elemtype);
|
|
MoveRetVTs.push_back(MVT::Other); MoveRetVTs.push_back(MVT::Glue);
|
|
std::vector<SDValue> MoveRetOps;
|
|
MoveRetOps.push_back(Chain);
|
|
MoveRetOps.push_back(DAG.getConstant(0, MVT::i32));
|
|
MoveRetOps.push_back(DAG.getConstant(paramNum, MVT::i32));
|
|
MoveRetOps.push_back(InFlag);
|
|
SDValue retval = DAG.getNode(NVPTXISD::LoadParam, dl, MoveRetVTs,
|
|
&MoveRetOps[0], MoveRetOps.size());
|
|
Chain = retval.getValue(1);
|
|
InFlag = retval.getValue(2);
|
|
tempRetVals.push_back(retval);
|
|
++paramNum;
|
|
}
|
|
if (Ins[i].VT.isVector())
|
|
InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, Ins[i].VT,
|
|
&tempRetVals[0], tempRetVals.size()));
|
|
else
|
|
InVals.push_back(tempRetVals[0]);
|
|
}
|
|
}
|
|
}
|
|
Chain = DAG.getCALLSEQ_END(Chain,
|
|
DAG.getIntPtrConstant(uniqueCallSite, true),
|
|
DAG.getIntPtrConstant(uniqueCallSite+1, true),
|
|
InFlag);
|
|
uniqueCallSite++;
|
|
|
|
// set isTailCall to false for now, until we figure out how to express
|
|
// tail call optimization in PTX
|
|
isTailCall = false;
|
|
return Chain;
|
|
}
|
|
#endif
|
|
|
|
// By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
|
|
// (see LegalizeDAG.cpp). This is slow and uses local memory.
|
|
// We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
|
|
SDValue NVPTXTargetLowering::
|
|
LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
|
|
SDNode *Node = Op.getNode();
|
|
DebugLoc dl = Node->getDebugLoc();
|
|
SmallVector<SDValue, 8> Ops;
|
|
unsigned NumOperands = Node->getNumOperands();
|
|
for (unsigned i=0; i < NumOperands; ++i) {
|
|
SDValue SubOp = Node->getOperand(i);
|
|
EVT VVT = SubOp.getNode()->getValueType(0);
|
|
EVT EltVT = VVT.getVectorElementType();
|
|
unsigned NumSubElem = VVT.getVectorNumElements();
|
|
for (unsigned j=0; j < NumSubElem; ++j) {
|
|
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
|
|
DAG.getIntPtrConstant(j)));
|
|
}
|
|
}
|
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
|
|
&Ops[0], Ops.size());
|
|
}
|
|
|
|
SDValue NVPTXTargetLowering::
|
|
LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
|
switch (Op.getOpcode()) {
|
|
case ISD::RETURNADDR: return SDValue();
|
|
case ISD::FRAMEADDR: return SDValue();
|
|
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
|
|
case ISD::INTRINSIC_W_CHAIN: return Op;
|
|
case ISD::BUILD_VECTOR:
|
|
case ISD::EXTRACT_SUBVECTOR:
|
|
return Op;
|
|
case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
|
|
default:
|
|
assert(0 && "Custom lowering not defined for operation");
|
|
}
|
|
}
|
|
|
|
SDValue
|
|
NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname, int idx,
|
|
EVT v) const {
|
|
std::string *name = nvTM->getManagedStrPool()->getManagedString(inname);
|
|
std::stringstream suffix;
|
|
suffix << idx;
|
|
*name += suffix.str();
|
|
return DAG.getTargetExternalSymbol(name->c_str(), v);
|
|
}
|
|
|
|
SDValue
|
|
NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
|
|
return getExtSymb(DAG, ".PARAM", idx, v);
|
|
}
|
|
|
|
SDValue
|
|
NVPTXTargetLowering::getParamHelpSymbol(SelectionDAG &DAG, int idx) {
|
|
return getExtSymb(DAG, ".HLPPARAM", idx);
|
|
}
|
|
|
|
// Check to see if the kernel argument is image*_t or sampler_t
|
|
|
|
bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
|
|
const char *specialTypes[] = {
|
|
"struct._image2d_t",
|
|
"struct._image3d_t",
|
|
"struct._sampler_t"
|
|
};
|
|
|
|
const Type *Ty = arg->getType();
|
|
const PointerType *PTy = dyn_cast<PointerType>(Ty);
|
|
|
|
if (!PTy)
|
|
return false;
|
|
|
|
if (!context)
|
|
return false;
|
|
|
|
const StructType *STy = dyn_cast<StructType>(PTy->getElementType());
|
|
const std::string TypeName = STy ? STy->getName() : "";
|
|
|
|
for (int i=0, e=sizeof(specialTypes)/sizeof(specialTypes[0]); i!=e; ++i)
|
|
if (TypeName == specialTypes[i])
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
SDValue
|
|
NVPTXTargetLowering::LowerFormalArguments(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
const TargetData *TD = getTargetData();
|
|
|
|
const Function *F = MF.getFunction();
|
|
const AttrListPtr &PAL = F->getAttributes();
|
|
|
|
SDValue Root = DAG.getRoot();
|
|
std::vector<SDValue> OutChains;
|
|
|
|
bool isKernel = llvm::isKernelFunction(*F);
|
|
bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
|
|
|
|
std::vector<Type *> argTypes;
|
|
std::vector<const Argument *> theArgs;
|
|
for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
|
|
I != E; ++I) {
|
|
theArgs.push_back(I);
|
|
argTypes.push_back(I->getType());
|
|
}
|
|
assert(argTypes.size() == Ins.size() &&
|
|
"Ins types and function types did not match");
|
|
|
|
int idx = 0;
|
|
for (unsigned i=0, e=Ins.size(); i!=e; ++i, ++idx) {
|
|
Type *Ty = argTypes[i];
|
|
EVT ObjectVT = getValueType(Ty);
|
|
assert(ObjectVT == Ins[i].VT &&
|
|
"Ins type did not match function type");
|
|
|
|
// If the kernel argument is image*_t or sampler_t, convert it to
|
|
// a i32 constant holding the parameter position. This can later
|
|
// matched in the AsmPrinter to output the correct mangled name.
|
|
if (isImageOrSamplerVal(theArgs[i],
|
|
(theArgs[i]->getParent() ?
|
|
theArgs[i]->getParent()->getParent() : 0))) {
|
|
assert(isKernel && "Only kernels can have image/sampler params");
|
|
InVals.push_back(DAG.getConstant(i+1, MVT::i32));
|
|
continue;
|
|
}
|
|
|
|
if (theArgs[i]->use_empty()) {
|
|
// argument is dead
|
|
InVals.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT));
|
|
continue;
|
|
}
|
|
|
|
// In the following cases, assign a node order of "idx+1"
|
|
// to newly created nodes. The SDNOdes for params have to
|
|
// appear in the same order as their order of appearance
|
|
// in the original function. "idx+1" holds that order.
|
|
if (PAL.paramHasAttr(i+1, Attribute::ByVal) == false) {
|
|
// A plain scalar.
|
|
if (isABI || isKernel) {
|
|
// If ABI, load from the param symbol
|
|
SDValue Arg = getParamSymbol(DAG, idx);
|
|
Value *srcValue = new Argument(PointerType::get(ObjectVT.getTypeForEVT(
|
|
F->getContext()),
|
|
llvm::ADDRESS_SPACE_PARAM));
|
|
SDValue p = DAG.getLoad(ObjectVT, dl, Root, Arg,
|
|
MachinePointerInfo(srcValue), false, false,
|
|
false,
|
|
TD->getABITypeAlignment(ObjectVT.getTypeForEVT(
|
|
F->getContext())));
|
|
if (p.getNode())
|
|
DAG.AssignOrdering(p.getNode(), idx+1);
|
|
InVals.push_back(p);
|
|
}
|
|
else {
|
|
// If no ABI, just move the param symbol
|
|
SDValue Arg = getParamSymbol(DAG, idx, ObjectVT);
|
|
SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
|
|
if (p.getNode())
|
|
DAG.AssignOrdering(p.getNode(), idx+1);
|
|
InVals.push_back(p);
|
|
}
|
|
continue;
|
|
}
|
|
|
|
// Param has ByVal attribute
|
|
if (isABI || isKernel) {
|
|
// Return MoveParam(param symbol).
|
|
// Ideally, the param symbol can be returned directly,
|
|
// but when SDNode builder decides to use it in a CopyToReg(),
|
|
// machine instruction fails because TargetExternalSymbol
|
|
// (not lowered) is target dependent, and CopyToReg assumes
|
|
// the source is lowered.
|
|
SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
|
|
SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
|
|
if (p.getNode())
|
|
DAG.AssignOrdering(p.getNode(), idx+1);
|
|
if (isKernel)
|
|
InVals.push_back(p);
|
|
else {
|
|
SDValue p2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
|
|
DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, MVT::i32),
|
|
p);
|
|
InVals.push_back(p2);
|
|
}
|
|
} else {
|
|
// Have to move a set of param symbols to registers and
|
|
// store them locally and return the local pointer in InVals
|
|
const PointerType *elemPtrType = dyn_cast<PointerType>(argTypes[i]);
|
|
assert(elemPtrType &&
|
|
"Byval parameter should be a pointer type");
|
|
Type *elemType = elemPtrType->getElementType();
|
|
// Compute the constituent parts
|
|
SmallVector<EVT, 16> vtparts;
|
|
SmallVector<uint64_t, 16> offsets;
|
|
ComputeValueVTs(*this, elemType, vtparts, &offsets, 0);
|
|
unsigned totalsize = 0;
|
|
for (unsigned j=0, je=vtparts.size(); j!=je; ++j)
|
|
totalsize += vtparts[j].getStoreSizeInBits();
|
|
SDValue localcopy = DAG.getFrameIndex(MF.getFrameInfo()->
|
|
CreateStackObject(totalsize/8, 16, false),
|
|
getPointerTy());
|
|
unsigned sizesofar = 0;
|
|
std::vector<SDValue> theChains;
|
|
for (unsigned j=0, je=vtparts.size(); j!=je; ++j) {
|
|
unsigned numElems = 1;
|
|
if (vtparts[j].isVector()) numElems = vtparts[j].getVectorNumElements();
|
|
for (unsigned k=0, ke=numElems; k!=ke; ++k) {
|
|
EVT tmpvt = vtparts[j];
|
|
if (tmpvt.isVector()) tmpvt = tmpvt.getVectorElementType();
|
|
SDValue arg = DAG.getNode(NVPTXISD::MoveParam, dl, tmpvt,
|
|
getParamSymbol(DAG, idx, tmpvt));
|
|
SDValue addr = DAG.getNode(ISD::ADD, dl, getPointerTy(), localcopy,
|
|
DAG.getConstant(sizesofar, getPointerTy()));
|
|
theChains.push_back(DAG.getStore(Chain, dl, arg, addr,
|
|
MachinePointerInfo(), false, false, 0));
|
|
sizesofar += tmpvt.getStoreSizeInBits()/8;
|
|
++idx;
|
|
}
|
|
}
|
|
--idx;
|
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &theChains[0],
|
|
theChains.size());
|
|
InVals.push_back(localcopy);
|
|
}
|
|
}
|
|
|
|
// Clang will check explicit VarArg and issue error if any. However, Clang
|
|
// will let code with
|
|
// implicit var arg like f() pass.
|
|
// We treat this case as if the arg list is empty.
|
|
//if (F.isVarArg()) {
|
|
// assert(0 && "VarArg not supported yet!");
|
|
//}
|
|
|
|
if (!OutChains.empty())
|
|
DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
|
&OutChains[0], OutChains.size()));
|
|
|
|
return Chain;
|
|
}
|
|
|
|
SDValue
|
|
NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
|
|
bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
DebugLoc dl, SelectionDAG &DAG) const {
|
|
|
|
bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
|
|
|
|
unsigned sizesofar = 0;
|
|
unsigned idx = 0;
|
|
for (unsigned i=0, e=Outs.size(); i!=e; ++i) {
|
|
SDValue theVal = OutVals[i];
|
|
EVT theValType = theVal.getValueType();
|
|
unsigned numElems = 1;
|
|
if (theValType.isVector()) numElems = theValType.getVectorNumElements();
|
|
for (unsigned j=0,je=numElems; j!=je; ++j) {
|
|
SDValue tmpval = theVal;
|
|
if (theValType.isVector())
|
|
tmpval = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
|
|
theValType.getVectorElementType(),
|
|
tmpval, DAG.getIntPtrConstant(j));
|
|
Chain = DAG.getNode(isABI ? NVPTXISD::StoreRetval :NVPTXISD::MoveToRetval,
|
|
dl, MVT::Other,
|
|
Chain,
|
|
DAG.getConstant(isABI ? sizesofar : idx, MVT::i32),
|
|
tmpval);
|
|
if (theValType.isVector())
|
|
sizesofar += theValType.getVectorElementType().getStoreSizeInBits()/8;
|
|
else
|
|
sizesofar += theValType.getStoreSizeInBits()/8;
|
|
++idx;
|
|
}
|
|
}
|
|
|
|
return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
|
|
}
|
|
|
|
void
|
|
NVPTXTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
|
|
std::string &Constraint,
|
|
std::vector<SDValue> &Ops,
|
|
SelectionDAG &DAG) const
|
|
{
|
|
if (Constraint.length() > 1)
|
|
return;
|
|
else
|
|
TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
|
|
}
|
|
|
|
// NVPTX suuport vector of legal types of any length in Intrinsics because the
|
|
// NVPTX specific type legalizer
|
|
// will legalize them to the PTX supported length.
|
|
bool
|
|
NVPTXTargetLowering::isTypeSupportedInIntrinsic(MVT VT) const {
|
|
if (isTypeLegal(VT))
|
|
return true;
|
|
if (VT.isVector()) {
|
|
MVT eVT = VT.getVectorElementType();
|
|
if (isTypeLegal(eVT))
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
|
|
// llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
|
|
// TgtMemIntrinsic
|
|
// because we need the information that is only available in the "Value" type
|
|
// of destination
|
|
// pointer. In particular, the address space information.
|
|
bool
|
|
NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo& Info, const CallInst &I,
|
|
unsigned Intrinsic) const {
|
|
switch (Intrinsic) {
|
|
default:
|
|
return false;
|
|
|
|
case Intrinsic::nvvm_atomic_load_add_f32:
|
|
Info.opc = ISD::INTRINSIC_W_CHAIN;
|
|
Info.memVT = MVT::f32;
|
|
Info.ptrVal = I.getArgOperand(0);
|
|
Info.offset = 0;
|
|
Info.vol = 0;
|
|
Info.readMem = true;
|
|
Info.writeMem = true;
|
|
Info.align = 0;
|
|
return true;
|
|
|
|
case Intrinsic::nvvm_atomic_load_inc_32:
|
|
case Intrinsic::nvvm_atomic_load_dec_32:
|
|
Info.opc = ISD::INTRINSIC_W_CHAIN;
|
|
Info.memVT = MVT::i32;
|
|
Info.ptrVal = I.getArgOperand(0);
|
|
Info.offset = 0;
|
|
Info.vol = 0;
|
|
Info.readMem = true;
|
|
Info.writeMem = true;
|
|
Info.align = 0;
|
|
return true;
|
|
|
|
case Intrinsic::nvvm_ldu_global_i:
|
|
case Intrinsic::nvvm_ldu_global_f:
|
|
case Intrinsic::nvvm_ldu_global_p:
|
|
|
|
Info.opc = ISD::INTRINSIC_W_CHAIN;
|
|
if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
|
|
Info.memVT = MVT::i32;
|
|
else if (Intrinsic == Intrinsic::nvvm_ldu_global_p)
|
|
Info.memVT = getPointerTy();
|
|
else
|
|
Info.memVT = MVT::f32;
|
|
Info.ptrVal = I.getArgOperand(0);
|
|
Info.offset = 0;
|
|
Info.vol = 0;
|
|
Info.readMem = true;
|
|
Info.writeMem = false;
|
|
Info.align = 0;
|
|
return true;
|
|
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// isLegalAddressingMode - Return true if the addressing mode represented
|
|
/// by AM is legal for this target, for a load/store of the specified type.
|
|
/// Used to guide target specific optimizations, like loop strength reduction
|
|
/// (LoopStrengthReduce.cpp) and memory optimization for address mode
|
|
/// (CodeGenPrepare.cpp)
|
|
bool
|
|
NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM,
|
|
Type *Ty) const {
|
|
|
|
// AddrMode - This represents an addressing mode of:
|
|
// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
|
|
//
|
|
// The legal address modes are
|
|
// - [avar]
|
|
// - [areg]
|
|
// - [areg+immoff]
|
|
// - [immAddr]
|
|
|
|
if (AM.BaseGV) {
|
|
if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
switch (AM.Scale) {
|
|
case 0: // "r", "r+i" or "i" is allowed
|
|
break;
|
|
case 1:
|
|
if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
|
|
return false;
|
|
// Otherwise we have r+i.
|
|
break;
|
|
default:
|
|
// No scale > 1 is allowed
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// NVPTX Inline Assembly Support
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
/// constraint it is for this target.
|
|
NVPTXTargetLowering::ConstraintType
|
|
NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
|
|
if (Constraint.size() == 1) {
|
|
switch (Constraint[0]) {
|
|
default:
|
|
break;
|
|
case 'r':
|
|
case 'h':
|
|
case 'c':
|
|
case 'l':
|
|
case 'f':
|
|
case 'd':
|
|
case '0':
|
|
case 'N':
|
|
return C_RegisterClass;
|
|
}
|
|
}
|
|
return TargetLowering::getConstraintType(Constraint);
|
|
}
|
|
|
|
|
|
std::pair<unsigned, const TargetRegisterClass*>
|
|
NVPTXTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
|
|
EVT VT) const {
|
|
if (Constraint.size() == 1) {
|
|
switch (Constraint[0]) {
|
|
case 'c':
|
|
return std::make_pair(0U, &NVPTX::Int8RegsRegClass);
|
|
case 'h':
|
|
return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
|
|
case 'r':
|
|
return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
|
|
case 'l':
|
|
case 'N':
|
|
return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
|
|
case 'f':
|
|
return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
|
|
case 'd':
|
|
return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
|
|
}
|
|
}
|
|
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
|
}
|
|
|
|
|
|
|
|
/// getFunctionAlignment - Return the Log2 alignment of this function.
|
|
unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
|
|
return 4;
|
|
}
|