mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183365 91177308-0d34-0410-b5e6-96231b3b80d8
791 lines
27 KiB
C++
791 lines
27 KiB
C++
//===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Defines an instruction selector for the AMDGPU target.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPUISelLowering.h" // For AMDGPUISD
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#include "AMDGPURegisterInfo.h"
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#include "AMDILDevices.h"
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#include "R600InstrInfo.h"
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#include "SIISelLowering.h"
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#include "llvm/ADT/ValueMap.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Support/Compiler.h"
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#include <list>
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#include <queue>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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/// AMDGPU specific code to select AMDGPU machine instructions for
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/// SelectionDAG operations.
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class AMDGPUDAGToDAGISel : public SelectionDAGISel {
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// Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
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// make the right decision when generating code for different targets.
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const AMDGPUSubtarget &Subtarget;
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public:
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AMDGPUDAGToDAGISel(TargetMachine &TM);
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virtual ~AMDGPUDAGToDAGISel();
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SDNode *Select(SDNode *N);
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virtual const char *getPassName() const;
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virtual void PostprocessISelDAG();
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private:
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inline SDValue getSmallIPtrImm(unsigned Imm);
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bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
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const R600InstrInfo *TII, std::vector<unsigned> Cst);
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bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
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bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
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// Complex pattern selectors
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bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
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bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
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bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
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static bool checkType(const Value *ptr, unsigned int addrspace);
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static const Value *getBasePointerValue(const Value *V);
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static bool isGlobalStore(const StoreSDNode *N);
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static bool isPrivateStore(const StoreSDNode *N);
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static bool isLocalStore(const StoreSDNode *N);
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static bool isRegionStore(const StoreSDNode *N);
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static bool isCPLoad(const LoadSDNode *N);
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static bool isConstantLoad(const LoadSDNode *N, int cbID);
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static bool isGlobalLoad(const LoadSDNode *N);
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static bool isParamLoad(const LoadSDNode *N);
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static bool isPrivateLoad(const LoadSDNode *N);
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static bool isLocalLoad(const LoadSDNode *N);
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static bool isRegionLoad(const LoadSDNode *N);
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bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
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bool SelectGlobalValueVariableOffset(SDValue Addr,
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SDValue &BaseReg, SDValue& Offset);
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bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
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// Include the pieces autogenerated from the target description.
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#include "AMDGPUGenDAGISel.inc"
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};
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} // end anonymous namespace
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/// \brief This pass converts a legalized DAG into a AMDGPU-specific
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// DAG, ready for instruction scheduling.
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FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
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) {
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return new AMDGPUDAGToDAGISel(TM);
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}
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AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM
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)
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: SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
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}
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AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
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}
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SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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bool AMDGPUDAGToDAGISel::SelectADDRParam(
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SDValue Addr, SDValue& R1, SDValue& R2) {
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if (Addr.getOpcode() == ISD::FrameIndex) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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}
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} else if (Addr.getOpcode() == ISD::ADD) {
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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}
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return true;
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}
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bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress) {
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return false;
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}
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return SelectADDRParam(Addr, R1, R2);
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}
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bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress) {
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return false;
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}
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if (Addr.getOpcode() == ISD::FrameIndex) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
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R2 = CurDAG->getTargetConstant(0, MVT::i64);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i64);
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}
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} else if (Addr.getOpcode() == ISD::ADD) {
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i64);
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}
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return true;
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}
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SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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unsigned int Opc = N->getOpcode();
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if (N->isMachineOpcode()) {
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return NULL; // Already selected.
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}
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switch (Opc) {
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default: break;
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case ISD::BUILD_VECTOR: {
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
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break;
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}
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// BUILD_VECTOR is usually lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
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// that adds a 128 bits reg copy when going through TwoAddressInstructions
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// pass. We want to avoid 128 bits copies as much as possible because they
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// can't be bundled by our scheduler.
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SDValue RegSeqArgs[9] = {
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CurDAG->getTargetConstant(AMDGPU::R600_Reg128RegClassID, MVT::i32),
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SDValue(), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
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SDValue(), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32),
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SDValue(), CurDAG->getTargetConstant(AMDGPU::sub2, MVT::i32),
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SDValue(), CurDAG->getTargetConstant(AMDGPU::sub3, MVT::i32)
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};
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bool IsRegSeq = true;
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for (unsigned i = 0; i < N->getNumOperands(); i++) {
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if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
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IsRegSeq = false;
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break;
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}
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RegSeqArgs[2 * i + 1] = N->getOperand(i);
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}
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if (!IsRegSeq)
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break;
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return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
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RegSeqArgs, 2 * N->getNumOperands() + 1);
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}
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case ISD::BUILD_PAIR: {
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SDValue RC, SubReg0, SubReg1;
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
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break;
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}
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if (N->getValueType(0) == MVT::i128) {
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RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
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SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
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SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
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} else if (N->getValueType(0) == MVT::i64) {
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RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
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SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
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SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
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} else {
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llvm_unreachable("Unhandled value type for BUILD_PAIR");
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}
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const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
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N->getOperand(1), SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
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SDLoc(N), N->getValueType(0), Ops);
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}
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case ISD::ConstantFP:
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case ISD::Constant: {
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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// XXX: Custom immediate lowering not implemented yet. Instead we use
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// pseudo instructions defined in SIInstructions.td
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if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
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break;
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}
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const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo());
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uint64_t ImmValue = 0;
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unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
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if (N->getOpcode() == ISD::ConstantFP) {
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// XXX: 64-bit Immediates not supported yet
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assert(N->getValueType(0) != MVT::f64);
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ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N);
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APFloat Value = C->getValueAPF();
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float FloatValue = Value.convertToFloat();
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if (FloatValue == 0.0) {
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ImmReg = AMDGPU::ZERO;
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} else if (FloatValue == 0.5) {
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ImmReg = AMDGPU::HALF;
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} else if (FloatValue == 1.0) {
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ImmReg = AMDGPU::ONE;
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} else {
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ImmValue = Value.bitcastToAPInt().getZExtValue();
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}
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} else {
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// XXX: 64-bit Immediates not supported yet
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assert(N->getValueType(0) != MVT::i64);
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
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if (C->getZExtValue() == 0) {
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ImmReg = AMDGPU::ZERO;
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} else if (C->getZExtValue() == 1) {
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ImmReg = AMDGPU::ONE_INT;
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} else {
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ImmValue = C->getZExtValue();
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}
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}
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for (SDNode::use_iterator Use = N->use_begin(), Next = llvm::next(Use);
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Use != SDNode::use_end(); Use = Next) {
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Next = llvm::next(Use);
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std::vector<SDValue> Ops;
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for (unsigned i = 0; i < Use->getNumOperands(); ++i) {
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Ops.push_back(Use->getOperand(i));
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}
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if (!Use->isMachineOpcode()) {
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if (ImmReg == AMDGPU::ALU_LITERAL_X) {
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// We can only use literal constants (e.g. AMDGPU::ZERO,
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// AMDGPU::ONE, etc) in machine opcodes.
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continue;
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}
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} else {
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if (!TII->isALUInstr(Use->getMachineOpcode()) ||
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(TII->get(Use->getMachineOpcode()).TSFlags &
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R600_InstFlag::VECTOR)) {
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continue;
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}
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int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), R600Operands::IMM);
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assert(ImmIdx != -1);
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// subtract one from ImmIdx, because the DST operand is usually index
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// 0 for MachineInstrs, but we have no DST in the Ops vector.
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ImmIdx--;
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// Check that we aren't already using an immediate.
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// XXX: It's possible for an instruction to have more than one
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// immediate operand, but this is not supported yet.
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if (ImmReg == AMDGPU::ALU_LITERAL_X) {
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(Use->getOperand(ImmIdx));
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assert(C);
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if (C->getZExtValue() != 0) {
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// This instruction is already using an immediate.
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continue;
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}
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// Set the immediate value
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Ops[ImmIdx] = CurDAG->getTargetConstant(ImmValue, MVT::i32);
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}
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}
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// Set the immediate register
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Ops[Use.getOperandNo()] = CurDAG->getRegister(ImmReg, MVT::i32);
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CurDAG->UpdateNodeOperands(*Use, Ops.data(), Use->getNumOperands());
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}
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break;
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}
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}
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SDNode *Result = SelectCode(N);
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// Fold operands of selected node
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
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const R600InstrInfo *TII =
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static_cast<const R600InstrInfo*>(TM.getInstrInfo());
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if (Result && Result->isMachineOpcode() && Result->getMachineOpcode() == AMDGPU::DOT_4) {
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bool IsModified = false;
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do {
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std::vector<SDValue> Ops;
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for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
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I != E; ++I)
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Ops.push_back(*I);
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IsModified = FoldDotOperands(Result->getMachineOpcode(), TII, Ops);
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if (IsModified) {
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Result = CurDAG->UpdateNodeOperands(Result, Ops.data(), Ops.size());
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}
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} while (IsModified);
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}
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if (Result && Result->isMachineOpcode() &&
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!(TII->get(Result->getMachineOpcode()).TSFlags & R600_InstFlag::VECTOR)
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&& TII->isALUInstr(Result->getMachineOpcode())) {
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// Fold FNEG/FABS/CONST_ADDRESS
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// TODO: Isel can generate multiple MachineInst, we need to recursively
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// parse Result
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bool IsModified = false;
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do {
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std::vector<SDValue> Ops;
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for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
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I != E; ++I)
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Ops.push_back(*I);
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IsModified = FoldOperands(Result->getMachineOpcode(), TII, Ops);
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if (IsModified) {
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Result = CurDAG->UpdateNodeOperands(Result, Ops.data(), Ops.size());
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}
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} while (IsModified);
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// If node has a single use which is CLAMP_R600, folds it
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if (Result->hasOneUse() && Result->isMachineOpcode()) {
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SDNode *PotentialClamp = *Result->use_begin();
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if (PotentialClamp->isMachineOpcode() &&
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PotentialClamp->getMachineOpcode() == AMDGPU::CLAMP_R600) {
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unsigned ClampIdx =
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TII->getOperandIdx(Result->getMachineOpcode(), R600Operands::CLAMP);
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std::vector<SDValue> Ops;
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unsigned NumOp = Result->getNumOperands();
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for (unsigned i = 0; i < NumOp; ++i) {
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Ops.push_back(Result->getOperand(i));
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}
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Ops[ClampIdx - 1] = CurDAG->getTargetConstant(1, MVT::i32);
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Result = CurDAG->SelectNodeTo(PotentialClamp,
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Result->getMachineOpcode(), PotentialClamp->getVTList(),
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Ops.data(), NumOp);
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}
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}
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}
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}
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return Result;
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}
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bool AMDGPUDAGToDAGISel::FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg,
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SDValue &Abs, const R600InstrInfo *TII,
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std::vector<unsigned> Consts) {
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switch (Src.getOpcode()) {
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case AMDGPUISD::CONST_ADDRESS: {
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SDValue CstOffset;
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if (Src.getValueType().isVector() ||
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!SelectGlobalValueConstantOffset(Src.getOperand(0), CstOffset))
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return false;
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ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(CstOffset);
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Consts.push_back(Cst->getZExtValue());
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if (!TII->fitsConstReadLimitations(Consts))
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return false;
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Src = CurDAG->getRegister(AMDGPU::ALU_CONST, MVT::f32);
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Sel = CstOffset;
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return true;
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}
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case ISD::FNEG:
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Src = Src.getOperand(0);
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Neg = CurDAG->getTargetConstant(1, MVT::i32);
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return true;
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case ISD::FABS:
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if (!Abs.getNode())
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return false;
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Src = Src.getOperand(0);
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Abs = CurDAG->getTargetConstant(1, MVT::i32);
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return true;
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case ISD::BITCAST:
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Src = Src.getOperand(0);
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return true;
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default:
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return false;
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}
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}
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bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
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const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
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int OperandIdx[] = {
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TII->getOperandIdx(Opcode, R600Operands::SRC0),
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TII->getOperandIdx(Opcode, R600Operands::SRC1),
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TII->getOperandIdx(Opcode, R600Operands::SRC2)
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};
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int SelIdx[] = {
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TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL),
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TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL),
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TII->getOperandIdx(Opcode, R600Operands::SRC2_SEL)
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};
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int NegIdx[] = {
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TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG),
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TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG),
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TII->getOperandIdx(Opcode, R600Operands::SRC2_NEG)
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};
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int AbsIdx[] = {
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TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS),
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TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS),
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-1
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};
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// Gather constants values
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std::vector<unsigned> Consts;
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for (unsigned j = 0; j < 3; j++) {
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int SrcIdx = OperandIdx[j];
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if (SrcIdx < 0)
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break;
|
|
if (RegisterSDNode *Reg = dyn_cast<RegisterSDNode>(Ops[SrcIdx - 1])) {
|
|
if (Reg->getReg() == AMDGPU::ALU_CONST) {
|
|
ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Ops[SelIdx[j] - 1]);
|
|
Consts.push_back(Cst->getZExtValue());
|
|
}
|
|
}
|
|
}
|
|
|
|
for (unsigned i = 0; i < 3; i++) {
|
|
if (OperandIdx[i] < 0)
|
|
return false;
|
|
SDValue &Src = Ops[OperandIdx[i] - 1];
|
|
SDValue &Sel = Ops[SelIdx[i] - 1];
|
|
SDValue &Neg = Ops[NegIdx[i] - 1];
|
|
SDValue FakeAbs;
|
|
SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
|
|
if (FoldOperand(Src, Sel, Neg, Abs, TII, Consts))
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::FoldDotOperands(unsigned Opcode,
|
|
const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
|
|
int OperandIdx[] = {
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_X),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_Y),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_Z),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_W),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_X),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_Y),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_Z),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_W)
|
|
};
|
|
int SelIdx[] = {
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL_X),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL_Y),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL_Z),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL_W),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL_X),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL_Y),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL_Z),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL_W)
|
|
};
|
|
int NegIdx[] = {
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG_X),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG_Y),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG_Z),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG_W),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG_X),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG_Y),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG_Z),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG_W)
|
|
};
|
|
int AbsIdx[] = {
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS_X),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS_Y),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS_Z),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS_W),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS_X),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS_Y),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS_Z),
|
|
TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS_W)
|
|
};
|
|
|
|
// Gather constants values
|
|
std::vector<unsigned> Consts;
|
|
for (unsigned j = 0; j < 8; j++) {
|
|
int SrcIdx = OperandIdx[j];
|
|
if (SrcIdx < 0)
|
|
break;
|
|
if (RegisterSDNode *Reg = dyn_cast<RegisterSDNode>(Ops[SrcIdx - 1])) {
|
|
if (Reg->getReg() == AMDGPU::ALU_CONST) {
|
|
ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Ops[SelIdx[j] - 1]);
|
|
Consts.push_back(Cst->getZExtValue());
|
|
}
|
|
}
|
|
}
|
|
|
|
for (unsigned i = 0; i < 8; i++) {
|
|
if (OperandIdx[i] < 0)
|
|
return false;
|
|
SDValue &Src = Ops[OperandIdx[i] - 1];
|
|
SDValue &Sel = Ops[SelIdx[i] - 1];
|
|
SDValue &Neg = Ops[NegIdx[i] - 1];
|
|
SDValue &Abs = Ops[AbsIdx[i] - 1];
|
|
if (FoldOperand(Src, Sel, Neg, Abs, TII, Consts))
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
|
|
if (!ptr) {
|
|
return false;
|
|
}
|
|
Type *ptrType = ptr->getType();
|
|
return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
|
|
}
|
|
|
|
const Value * AMDGPUDAGToDAGISel::getBasePointerValue(const Value *V) {
|
|
if (!V) {
|
|
return NULL;
|
|
}
|
|
const Value *ret = NULL;
|
|
ValueMap<const Value *, bool> ValueBitMap;
|
|
std::queue<const Value *, std::list<const Value *> > ValueQueue;
|
|
ValueQueue.push(V);
|
|
while (!ValueQueue.empty()) {
|
|
V = ValueQueue.front();
|
|
if (ValueBitMap.find(V) == ValueBitMap.end()) {
|
|
ValueBitMap[V] = true;
|
|
if (dyn_cast<Argument>(V) && dyn_cast<PointerType>(V->getType())) {
|
|
ret = V;
|
|
break;
|
|
} else if (dyn_cast<GlobalVariable>(V)) {
|
|
ret = V;
|
|
break;
|
|
} else if (dyn_cast<Constant>(V)) {
|
|
const ConstantExpr *CE = dyn_cast<ConstantExpr>(V);
|
|
if (CE) {
|
|
ValueQueue.push(CE->getOperand(0));
|
|
}
|
|
} else if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
|
|
ret = AI;
|
|
break;
|
|
} else if (const Instruction *I = dyn_cast<Instruction>(V)) {
|
|
uint32_t numOps = I->getNumOperands();
|
|
for (uint32_t x = 0; x < numOps; ++x) {
|
|
ValueQueue.push(I->getOperand(x));
|
|
}
|
|
} else {
|
|
assert(!"Found a Value that we didn't know how to handle!");
|
|
}
|
|
}
|
|
ValueQueue.pop();
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
|
|
return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
|
|
return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
|
|
&& !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
|
|
&& !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
|
|
return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
|
|
return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
|
|
if (checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)) {
|
|
return true;
|
|
}
|
|
MachineMemOperand *MMO = N->getMemOperand();
|
|
const Value *V = MMO->getValue();
|
|
const Value *BV = getBasePointerValue(V);
|
|
if (MMO
|
|
&& MMO->getValue()
|
|
&& ((V && dyn_cast<GlobalValue>(V))
|
|
|| (BV && dyn_cast<GlobalValue>(
|
|
getBasePointerValue(MMO->getValue()))))) {
|
|
return checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS);
|
|
} else {
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) {
|
|
return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) {
|
|
return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) {
|
|
return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) {
|
|
return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
|
|
MachineMemOperand *MMO = N->getMemOperand();
|
|
if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
|
|
if (MMO) {
|
|
const Value *V = MMO->getValue();
|
|
const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
|
|
if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) {
|
|
if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
|
|
// Check to make sure we are not a constant pool load or a constant load
|
|
// that is marked as a private load
|
|
if (isCPLoad(N) || isConstantLoad(N, -1)) {
|
|
return false;
|
|
}
|
|
}
|
|
if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
|
|
&& !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
|
|
&& !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
|
|
&& !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
|
|
&& !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
|
|
&& !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
const char *AMDGPUDAGToDAGISel::getPassName() const {
|
|
return "AMDGPU DAG->DAG Pattern Instruction Selection";
|
|
}
|
|
|
|
#ifdef DEBUGTMP
|
|
#undef INT64_C
|
|
#endif
|
|
#undef DEBUGTMP
|
|
|
|
///==== AMDGPU Functions ====///
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
|
|
SDValue& IntPtr) {
|
|
if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
|
|
IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
|
|
SDValue& BaseReg, SDValue &Offset) {
|
|
if (!dyn_cast<ConstantSDNode>(Addr)) {
|
|
BaseReg = Addr;
|
|
Offset = CurDAG->getIntPtrConstant(0, true);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
ConstantSDNode * IMMOffset;
|
|
|
|
if (Addr.getOpcode() == ISD::ADD
|
|
&& (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
|
|
&& isInt<16>(IMMOffset->getZExtValue())) {
|
|
|
|
Base = Addr.getOperand(0);
|
|
Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
|
|
return true;
|
|
// If the pointer address is constant, we can move it to the offset field.
|
|
} else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
|
|
&& isInt<16>(IMMOffset->getZExtValue())) {
|
|
Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
|
|
SDLoc(CurDAG->getEntryNode()),
|
|
AMDGPU::ZERO, MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
// Default case, no offset
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
ConstantSDNode *C;
|
|
|
|
if ((C = dyn_cast<ConstantSDNode>(Addr))) {
|
|
Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
|
|
} else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
|
|
(C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
|
|
Base = Addr.getOperand(0);
|
|
Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
|
|
} else {
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
|
|
|
|
if (Subtarget.device()->getGeneration() < AMDGPUDeviceInfo::HD7XXX) {
|
|
return;
|
|
}
|
|
|
|
// Go over all selected nodes and try to fold them a bit more
|
|
const AMDGPUTargetLowering& Lowering = (*(const AMDGPUTargetLowering*)TLI);
|
|
for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
|
|
E = CurDAG->allnodes_end(); I != E; ++I) {
|
|
|
|
SDNode *Node = I;
|
|
switch (Node->getOpcode()) {
|
|
// Fix the register class in copy to CopyToReg nodes - ISel will always
|
|
// use SReg classes for 64-bit copies, but this is not always what we want.
|
|
case ISD::CopyToReg: {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
|
SDValue Val = Node->getOperand(2);
|
|
const TargetRegisterClass *RC = RegInfo->getRegClass(Reg);
|
|
if (RC != &AMDGPU::SReg_64RegClass) {
|
|
continue;
|
|
}
|
|
|
|
if (!Val.getNode()->isMachineOpcode()) {
|
|
continue;
|
|
}
|
|
|
|
const MCInstrDesc Desc = TM.getInstrInfo()->get(Val.getNode()->getMachineOpcode());
|
|
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
|
|
RegInfo->setRegClass(Reg, TRI->getRegClass(Desc.OpInfo[0].RegClass));
|
|
continue;
|
|
}
|
|
}
|
|
|
|
MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
|
|
if (!MachineNode)
|
|
continue;
|
|
|
|
SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
|
|
if (ResNode != Node) {
|
|
ReplaceUses(Node, ResNode);
|
|
}
|
|
}
|
|
}
|