Bruno Cardoso Lopes cea34e41fa The vpermilps and vpermilpd have different behaviour regarding the ... usage of the shuffle bitmask. Both work in 128-bit lanes without crossing, but in the former the mask of the high part is the same used by the low part while in the later both lanes have independent masks. Handle this properly and and add support for vpermilpd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136200 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-27 00:56:34 +00:00
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Analysis	Fix AliasSetTracker so that it doesn't make any assumptions about instructions it doesn't know about (like the atomic instructions I'm adding).	2011-07-27 00:46:46 +00:00
Archive
AsmParser	Initial implementation of 'fence' instruction, the new C++0x-style replacement for llvm.memory.barrier.	2011-07-25 23:16:38 +00:00
Bitcode	Initial implementation of 'fence' instruction, the new C++0x-style replacement for llvm.memory.barrier.	2011-07-25 23:16:38 +00:00
CodeGen	It is quiet possible that inlined function body is split into multiple chunks of consequtive instructions. But, there is not any way to describe this in .debug_inline accelerator table used by gdb. However, describe non contiguous ranges of inlined function body appropriately using AT_range of DW_TAG_inlined_subroutine debug info entry.	2011-07-27 00:34:13 +00:00
CompilerDriver
ExecutionEngine
Linker
MC	Support .code32 and .code64 in X86 assembler.	2011-07-27 00:38:12 +00:00
Object
Support	Teach the Triple class about kfreebsd (FreeBSD kernel with	2011-07-26 15:30:04 +00:00
Target	The vpermilps and vpermilpd have different behaviour regarding the	2011-07-27 00:56:34 +00:00
Transforms	Use the correct for for the version. It's little endian and my brain is	2011-07-26 18:31:41 +00:00
VMCore	Initial implementation of 'fence' instruction, the new C++0x-style replacement for llvm.memory.barrier.	2011-07-25 23:16:38 +00:00
CMakeLists.txt
Makefile