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https://github.com/c64scene-ar/llvm-6502.git
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0261cea689
Changing ARMBaseTargetMachine to return ARMTargetLowering intead of the generic one (similar to x86 code). Tests showing which instructions were added to cast when necessary or cost zero when not. Downcast to 16 bits are not lowered in NEON, so costs are not there yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173849 91177308-0d34-0410-b5e6-96231b3b80d8
115 lines
3.4 KiB
LLVM
115 lines
3.4 KiB
LLVM
; RUN: opt < %s -cost-model -analyze -mtriple=armv7-linux-gnueabihf -mcpu=cortex-a9 | FileCheck --check-prefix=COST %s
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; To see the assembly output: llc -mcpu=cortex-a9 < %s | FileCheck --check-prefix=ASM %s
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; ASM lines below are only for reference, tests on that direction should go to tests/CodeGen/ARM
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; ModuleID = 'arm.ll'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
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target triple = "armv7--linux-gnueabihf"
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%T216 = type <2 x i16>
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%T232 = type <2 x i32>
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%T264 = type <2 x i64>
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%T416 = type <4 x i16>
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%T432 = type <4 x i32>
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%T464 = type <4 x i64>
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define void @direct(%T432* %loadaddr, %T432* %loadaddr2, %T432* %storeaddr) {
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; COST: function 'direct':
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%v0 = load %T432* %loadaddr
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; ASM: vld1.64
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%v1 = load %T432* %loadaddr2
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; ASM: vld1.64
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%r3 = mul %T432 %v0, %v1
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; COST: cost of 2 for instruction: {{.*}} mul <4 x i32>
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; ASM: vmul.i32
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store %T432 %r3, %T432* %storeaddr
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; ASM: vst1.64
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ret void
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}
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define void @ups1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
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; COST: function 'ups1632':
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%v0 = load %T416* %loadaddr
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; ASM: vldr
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%v1 = load %T416* %loadaddr2
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; ASM: vldr
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%r1 = sext %T416 %v0 to %T432
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%r2 = sext %T416 %v1 to %T432
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; COST: cost of 0 for instruction: {{.*}} sext <4 x i16> {{.*}} to <4 x i32>
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%r3 = mul %T432 %r1, %r2
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; COST: cost of 2 for instruction: {{.*}} mul <4 x i32>
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; ASM: vmull.s16
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store %T432 %r3, %T432* %storeaddr
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; ASM: vst1.64
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ret void
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}
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define void @upu1632(%T416* %loadaddr, %T416* %loadaddr2, %T432* %storeaddr) {
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; COST: function 'upu1632':
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%v0 = load %T416* %loadaddr
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; ASM: vldr
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%v1 = load %T416* %loadaddr2
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; ASM: vldr
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%r1 = zext %T416 %v0 to %T432
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%r2 = zext %T416 %v1 to %T432
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; COST: cost of 0 for instruction: {{.*}} zext <4 x i16> {{.*}} to <4 x i32>
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%r3 = mul %T432 %r1, %r2
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; COST: cost of 2 for instruction: {{.*}} mul <4 x i32>
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; ASM: vmull.u16
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store %T432 %r3, %T432* %storeaddr
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; ASM: vst1.64
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ret void
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}
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define void @ups3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
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; COST: function 'ups3264':
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%v0 = load %T232* %loadaddr
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; ASM: vldr
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%v1 = load %T232* %loadaddr2
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; ASM: vldr
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%r3 = mul %T232 %v0, %v1
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; ASM: vmul.i32
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; COST: cost of 1 for instruction: {{.*}} mul <2 x i32>
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%st = sext %T232 %r3 to %T264
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; ASM: vmovl.s32
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; COST: cost of 1 for instruction: {{.*}} sext <2 x i32> {{.*}} to <2 x i64>
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store %T264 %st, %T264* %storeaddr
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; ASM: vst1.64
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ret void
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}
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define void @upu3264(%T232* %loadaddr, %T232* %loadaddr2, %T264* %storeaddr) {
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; COST: function 'upu3264':
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%v0 = load %T232* %loadaddr
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; ASM: vldr
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%v1 = load %T232* %loadaddr2
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; ASM: vldr
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%r3 = mul %T232 %v0, %v1
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; ASM: vmul.i32
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; COST: cost of 1 for instruction: {{.*}} mul <2 x i32>
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%st = zext %T232 %r3 to %T264
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; ASM: vmovl.u32
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; COST: cost of 1 for instruction: {{.*}} zext <2 x i32> {{.*}} to <2 x i64>
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store %T264 %st, %T264* %storeaddr
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; ASM: vst1.64
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ret void
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}
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define void @dn3216(%T432* %loadaddr, %T432* %loadaddr2, %T416* %storeaddr) {
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; COST: function 'dn3216':
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%v0 = load %T432* %loadaddr
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; ASM: vld1.64
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%v1 = load %T432* %loadaddr2
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; ASM: vld1.64
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%r3 = mul %T432 %v0, %v1
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; ASM: vmul.i32
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; COST: cost of 2 for instruction: {{.*}} mul <4 x i32>
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%st = trunc %T432 %r3 to %T416
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; ASM: vmovn.i32
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; COST: cost of 1 for instruction: {{.*}} trunc <4 x i32> {{.*}} to <4 x i16>
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store %T416 %st, %T416* %storeaddr
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; ASM: vstr
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ret void
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}
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