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https://github.com/c64scene-ar/llvm-6502.git
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8dc440a46a
Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8
89 lines
4.6 KiB
TableGen
89 lines
4.6 KiB
TableGen
//===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the G4+ (7450) processor.
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//
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//===----------------------------------------------------------------------===//
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def IU3 : FuncUnit; // integer unit 3 (7450 simple)
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def IU4 : FuncUnit; // integer unit 4 (7450 simple)
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def G4PlusItineraries : ProcessorItineraries<
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[IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [
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InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>,
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InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>,
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InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>,
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InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
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InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>,
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InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>,
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InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>,
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InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
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InstrItinData<BrCR , [InstrStage<2, [IU2]>]>,
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InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>,
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InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>,
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InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLoadUpd , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStStoreUpd, [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>,
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InstrItinData<LdStSTFD , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStSTFDU , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>,
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InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>,
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InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLHAU , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>,
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InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStSTDU , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
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InstrItinData<SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<SprMFSR , [InstrStage<4, [IU2]>]>,
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InstrItinData<SprMTMSR , [InstrStage<2, [IU2]>]>,
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InstrItinData<SprMTSR , [InstrStage<2, [IU2]>]>,
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InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>,
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InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>,
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InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>,
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InstrItinData<SprMFSPR , [InstrStage<4, [IU2]>]>,
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InstrItinData<SprMFTB , [InstrStage<5, [IU2]>]>,
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InstrItinData<SprMTSPR , [InstrStage<2, [IU2]>]>,
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InstrItinData<SprMTSRIN , [InstrStage<2, [IU2]>]>,
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InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
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InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>,
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InstrItinData<FPAddSub , [InstrStage<5, [FPU1]>]>,
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InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>,
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InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>,
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InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>,
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InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>,
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InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>,
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InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
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InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
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InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
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InstrItinData<VecComplex , [InstrStage<4, [VIU2]>]>,
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InstrItinData<VecPerm , [InstrStage<2, [VPU]>]>,
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InstrItinData<VecFPRound , [InstrStage<4, [VIU1]>]>,
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InstrItinData<VecVSL , [InstrStage<2, [VPU]>]>,
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InstrItinData<VecVSR , [InstrStage<2, [VPU]>]>
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]>;
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