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https://github.com/c64scene-ar/llvm-6502.git
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1c84e2a7d3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1201 91177308-0d34-0410-b5e6-96231b3b80d8
399 lines
12 KiB
C++
399 lines
12 KiB
C++
//===-- llvm/Target/SchedInfo.h - Target Instruction Sched Info --*- C++ -*-==//
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//
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// This file describes the target machine to the instruction scheduler.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_MACHINESCHEDINFO_H
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#define LLVM_TARGET_MACHINESCHEDINFO_H
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#include "llvm/Target/MachineInstrInfo.h"
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#include <hash_map>
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typedef long long cycles_t;
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const cycles_t HUGE_LATENCY = ~((unsigned long long) 1 << sizeof(cycles_t)-1);
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const cycles_t INVALID_LATENCY = -HUGE_LATENCY;
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static const unsigned MAX_OPCODE_SIZE = 16;
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class OpCodePair {
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public:
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long val; // make long by concatenating two opcodes
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OpCodePair(MachineOpCode op1, MachineOpCode op2)
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: val((op1 < 0 || op2 < 0)?
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-1 : (long)((((unsigned) op1) << MAX_OPCODE_SIZE) | (unsigned) op2)) {}
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bool operator==(const OpCodePair& op) const {
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return val == op.val;
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}
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private:
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OpCodePair(); // disable for now
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};
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template <> struct hash<OpCodePair> {
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size_t operator()(const OpCodePair& pair) const {
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return hash<long>()(pair.val);
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}
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};
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//---------------------------------------------------------------------------
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// class MachineResource
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// class CPUResource
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//
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// Purpose:
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// Representation of a single machine resource used in specifying
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// resource usages of machine instructions for scheduling.
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//---------------------------------------------------------------------------
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typedef unsigned int resourceId_t;
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class MachineResource {
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public:
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const string rname;
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resourceId_t rid;
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/*ctor*/ MachineResource(const string& resourceName)
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: rname(resourceName), rid(nextId++) {}
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private:
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static resourceId_t nextId;
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MachineResource(); // disable
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};
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class CPUResource : public MachineResource {
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public:
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int maxNumUsers; // MAXINT if no restriction
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/*ctor*/ CPUResource(const string& rname, int maxUsers)
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: MachineResource(rname), maxNumUsers(maxUsers) {}
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};
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//---------------------------------------------------------------------------
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// struct InstrClassRUsage
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// struct InstrRUsageDelta
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// struct InstrIssueDelta
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// struct InstrRUsage
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//
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// Purpose:
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// The first three are structures used to specify machine resource
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// usages for each instruction in a machine description file:
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// InstrClassRUsage : resource usages common to all instrs. in a class
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// InstrRUsageDelta : add/delete resource usage for individual instrs.
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// InstrIssueDelta : add/delete instr. issue info for individual instrs
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//
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// The last one (InstrRUsage) is the internal representation of
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// instruction resource usage constructed from the above three.
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//---------------------------------------------------------------------------
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const int MAX_NUM_SLOTS = 32;
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const int MAX_NUM_CYCLES = 32;
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struct InstrClassRUsage {
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InstrSchedClass schedClass;
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int totCycles;
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// Issue restrictions common to instructions in this class
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unsigned int maxNumIssue;
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bool isSingleIssue;
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bool breaksGroup;
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cycles_t numBubbles;
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// Feasible slots to use for instructions in this class.
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// The size of vector S[] is `numSlots'.
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unsigned int numSlots;
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unsigned int feasibleSlots[MAX_NUM_SLOTS];
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// Resource usages common to instructions in this class.
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// The size of vector V[] is `numRUEntries'.
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unsigned int numRUEntries;
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struct {
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resourceId_t resourceId;
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unsigned int startCycle;
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int numCycles;
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} V[MAX_NUM_CYCLES];
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};
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struct InstrRUsageDelta {
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MachineOpCode opCode;
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resourceId_t resourceId;
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unsigned int startCycle;
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int numCycles;
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};
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// Specify instruction issue restrictions for individual instructions
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// that differ from the common rules for the class.
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//
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struct InstrIssueDelta {
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MachineOpCode opCode;
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bool isSingleIssue;
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bool breaksGroup;
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cycles_t numBubbles;
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};
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struct InstrRUsage {
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/*ctor*/ InstrRUsage () {}
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/*ctor*/ InstrRUsage (const InstrRUsage& instrRU);
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InstrRUsage& operator= (const InstrRUsage& instrRU);
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bool sameAsClass;
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// Issue restrictions for this instruction
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bool isSingleIssue;
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bool breaksGroup;
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cycles_t numBubbles;
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// Feasible slots to use for this instruction.
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vector<bool> feasibleSlots;
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// Resource usages for this instruction, with one resource vector per cycle.
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cycles_t numCycles;
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vector<vector<resourceId_t> > resourcesByCycle;
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private:
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// Conveniences for initializing this structure
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InstrRUsage& operator= (const InstrClassRUsage& classRU);
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void addIssueDelta (const InstrIssueDelta& delta);
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void addUsageDelta (const InstrRUsageDelta& delta);
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void setMaxSlots (int maxNumSlots);
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friend class MachineSchedInfo; // give access to these functions
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};
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inline void
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InstrRUsage::setMaxSlots(int maxNumSlots)
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{
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feasibleSlots.resize(maxNumSlots);
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}
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inline InstrRUsage&
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InstrRUsage::operator=(const InstrRUsage& instrRU)
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{
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sameAsClass = instrRU.sameAsClass;
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isSingleIssue = instrRU.isSingleIssue;
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breaksGroup = instrRU.breaksGroup;
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numBubbles = instrRU.numBubbles;
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feasibleSlots = instrRU.feasibleSlots;
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numCycles = instrRU.numCycles;
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resourcesByCycle = instrRU.resourcesByCycle;
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return *this;
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}
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inline /*ctor*/
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InstrRUsage::InstrRUsage(const InstrRUsage& instrRU)
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{
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*this = instrRU;
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}
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inline InstrRUsage&
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InstrRUsage::operator=(const InstrClassRUsage& classRU)
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{
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sameAsClass = true;
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isSingleIssue = classRU.isSingleIssue;
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breaksGroup = classRU.breaksGroup;
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numBubbles = classRU.numBubbles;
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for (unsigned i=0; i < classRU.numSlots; i++)
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{
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unsigned slot = classRU.feasibleSlots[i];
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assert(slot < feasibleSlots.size() && "Invalid slot specified!");
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this->feasibleSlots[slot] = true;
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}
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this->numCycles = classRU.totCycles;
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this->resourcesByCycle.resize(this->numCycles);
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for (unsigned i=0; i < classRU.numRUEntries; i++)
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for (unsigned c=classRU.V[i].startCycle, NC = c + classRU.V[i].numCycles;
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c < NC; c++)
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this->resourcesByCycle[c].push_back(classRU.V[i].resourceId);
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// Sort each resource usage vector by resourceId_t to speed up conflict checking
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for (unsigned i=0; i < this->resourcesByCycle.size(); i++)
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sort(resourcesByCycle[i].begin(), resourcesByCycle[i].end());
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return *this;
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}
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inline void
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InstrRUsage::addIssueDelta(const InstrIssueDelta& delta)
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{
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sameAsClass = false;
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isSingleIssue = delta.isSingleIssue;
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breaksGroup = delta.breaksGroup;
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numBubbles = delta.numBubbles;
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}
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// Add the extra resource usage requirements specified in the delta.
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// Note that a negative value of `numCycles' means one entry for that
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// resource should be deleted for each cycle.
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//
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inline void
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InstrRUsage::addUsageDelta(const InstrRUsageDelta& delta)
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{
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int NC = delta.numCycles;
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this->sameAsClass = false;
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// resize the resources vector if more cycles are specified
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unsigned maxCycles = this->numCycles;
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maxCycles = max(maxCycles, delta.startCycle + abs(NC) - 1);
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if (maxCycles > this->numCycles)
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{
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this->resourcesByCycle.resize(maxCycles);
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this->numCycles = maxCycles;
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}
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if (NC >= 0)
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for (unsigned c=delta.startCycle, last=c+NC-1; c <= last; c++)
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this->resourcesByCycle[c].push_back(delta.resourceId);
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else
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// Remove the resource from all NC cycles.
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for (unsigned c=delta.startCycle, last=(c-NC)-1; c <= last; c++)
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{
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// Look for the resource backwards so we remove the last entry
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// for that resource in each cycle.
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vector<resourceId_t>& rvec = this->resourcesByCycle[c];
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int r;
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for (r = (int) rvec.size(); r >= 0; r--)
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if (rvec[r] == delta.resourceId)
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{// found last entry for the resource
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rvec.erase(rvec.begin() + r);
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break;
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}
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assert(r >= 0 && "Resource to remove was unused in cycle c!");
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}
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}
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//---------------------------------------------------------------------------
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// class MachineSchedInfo
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//
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// Purpose:
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// Common interface to machine information for instruction scheduling
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//---------------------------------------------------------------------------
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class MachineSchedInfo : public NonCopyableV {
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public:
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const TargetMachine& target;
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unsigned int maxNumIssueTotal;
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int longestIssueConflict;
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int branchMispredictPenalty; // 4 for SPARC IIi
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int branchTargetUnknownPenalty; // 2 for SPARC IIi
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int l1DCacheMissPenalty; // 7 or 9 for SPARC IIi
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int l1ICacheMissPenalty; // ? for SPARC IIi
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bool inOrderLoads; // true for SPARC IIi
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bool inOrderIssue; // true for SPARC IIi
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bool inOrderExec; // false for most architectures
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bool inOrderRetire; // true for most architectures
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protected:
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inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
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assert(opCode >= 0 && opCode < (int) instrRUsages.size());
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return instrRUsages[opCode];
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}
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inline const InstrClassRUsage&
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getClassRUsage(const InstrSchedClass& sc) const {
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assert(sc >= 0 && sc < numSchedClasses);
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return classRUsages[sc];
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}
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public:
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/*ctor*/ MachineSchedInfo (const TargetMachine& tgt,
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int _numSchedClasses,
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const InstrClassRUsage* _classRUsages,
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const InstrRUsageDelta* _usageDeltas,
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const InstrIssueDelta* _issueDeltas,
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unsigned int _numUsageDeltas,
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unsigned int _numIssueDeltas);
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/*dtor*/ virtual ~MachineSchedInfo () {}
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inline const MachineInstrInfo& getInstrInfo() const {
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return *mii;
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}
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inline int getNumSchedClasses() const {
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return numSchedClasses;
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}
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inline unsigned int getMaxNumIssueTotal() const {
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return maxNumIssueTotal;
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}
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inline unsigned int getMaxIssueForClass(const InstrSchedClass& sc) const {
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assert(sc >= 0 && sc < numSchedClasses);
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return classRUsages[sc].maxNumIssue;
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}
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inline InstrSchedClass getSchedClass (MachineOpCode opCode) const {
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return getInstrInfo().getSchedClass(opCode);
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}
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inline bool instrCanUseSlot (MachineOpCode opCode,
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unsigned s) const {
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assert(s < getInstrRUsage(opCode).feasibleSlots.size() && "Invalid slot!");
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return getInstrRUsage(opCode).feasibleSlots[s];
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}
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inline int getLongestIssueConflict () const {
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return longestIssueConflict;
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}
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inline int getMinIssueGap (MachineOpCode fromOp,
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MachineOpCode toOp) const {
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hash_map<OpCodePair,int>::const_iterator
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I = issueGaps.find(OpCodePair(fromOp, toOp));
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return (I == issueGaps.end())? 0 : (*I).second;
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}
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inline const vector<MachineOpCode>*
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getConflictList(MachineOpCode opCode) const {
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hash_map<MachineOpCode,vector<MachineOpCode> >::const_iterator
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I = conflictLists.find(opCode);
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return (I == conflictLists.end())? NULL : & (*I).second;
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}
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inline bool isSingleIssue (MachineOpCode opCode) const {
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return getInstrRUsage(opCode).isSingleIssue;
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}
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inline bool breaksIssueGroup (MachineOpCode opCode) const {
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return getInstrRUsage(opCode).breaksGroup;
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}
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inline unsigned int numBubblesAfter (MachineOpCode opCode) const {
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return getInstrRUsage(opCode).numBubbles;
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}
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protected:
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virtual void initializeResources ();
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private:
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void computeInstrResources(const vector<InstrRUsage>& instrRUForClasses);
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void computeIssueGaps(const vector<InstrRUsage>& instrRUForClasses);
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protected:
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int numSchedClasses;
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const MachineInstrInfo* mii;
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const InstrClassRUsage* classRUsages; // raw array by sclass
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const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
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const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
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unsigned int numUsageDeltas;
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unsigned int numIssueDeltas;
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vector<InstrRUsage> instrRUsages; // indexed by opcode
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hash_map<OpCodePair,int> issueGaps; // indexed by opcode pair
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hash_map<MachineOpCode,vector<MachineOpCode> >
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conflictLists; // indexed by opcode
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};
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#endif
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