Bill Wendling 47e208bbea Try to eliminate the use of the 'unwind' instruction. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139046 91177308-0d34-0410-b5e6-96231b3b80d8		2011-09-02 22:41:11 +00:00
..
Alpha
ARM	Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.	2011-09-02 22:33:24 +00:00
Blackfin
CBackend
CellSPU	Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.	2011-09-02 10:05:01 +00:00
CPP
Generic	Try to eliminate the use of the 'unwind' instruction.	2011-09-02 22:41:11 +00:00
MBlaze
Mips	Better fix for this testcase. Update it to the new EH scheme entirely.	2011-09-02 21:27:08 +00:00
MSP430
PowerPC	Update more tests to the new EH scheme.	2011-08-31 21:04:11 +00:00
PTX
SPARC
SystemZ
Thumb	Revert r131152, r129796, r129761. This code is currently considered	2011-09-01 23:07:08 +00:00
Thumb2	Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical	2011-08-30 01:34:54 +00:00
X86	Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.	2011-09-02 22:33:24 +00:00
XCore	Add Uses=[SP] to call instructions. This fixes a miscompilation with a	2011-08-24 13:32:43 +00:00